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PDF TC59LM806CFT Data sheet ( Hoja de datos )

Número de pieza TC59LM806CFT
Descripción (TC59LM806CFT / TC59LM814CFT) 256M-bits Network FCRAM1
Fabricantes Toshiba Semiconductor 
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No Preview Available ! TC59LM806CFT Hoja de datos, Descripción, Manual

( DataSheet : www.DataSheet4U.com )
TC59LM814/06CFT-50,-60
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
256Mbits Network FCRAM1
4,194,304-WORDS × 4 BANKS × 16-BITS
8,388,608-WORDS × 4 BANKS × 8-BITS
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM814/06CFT are Network
FCRAMTM containing 268,435,456 memory cells. TC59LM814CFT is organized as 4,194,304-words × 4 banks s× 16
bits, TC59LM806CFT is organized as 8,388,608 words × 4 banks × 8 bits. TC59LM814/06CFT feature a fully
synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. TC59LM814/06CFT can operate fast core cycle
using the FCRAMTM core architecture compared with regular DDR SDRAM.
TC59LM814/06CFT is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
FEATURES
PARAMETER
TC59LM814/06
-50 -60
tCK Clock Cycle Time (min)
CL = 3
CL = 4
5.5 ns
5 ns
6.5 ns
6 ns
tRC Random Read/Write Cycle Time (min)
25 ns
30 ns
tRAC Random Access Time (max)
22 ns
26 ns
IDD1S Operating Current (single bank) (max)
190 mA
170 mA
lDD2P Power Down Current (max)
2 mA
2 mA
lDD6 Self-Refresh Current (max)
3 mA
3 mA
Fully Synchronous Operation
Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
Fast clock cycle time of 5 ns minimum
Clock: 200 MHz maximum
Data: 400 Mbps/pin maximum
Quad Independent Banks operation
Fast cycle and Short Latency
Bidirectional Data Strobe Signal
Distributed Auto-Refresh cycle in 7.8 µs
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
CAS Latency = 3, 4
Burst Length = 2, 4
Organization TC59LM814CFT: 4,194,304 words × 4 banks × 16 bits
TC59LM806CFT: 8,388,608 words × 4 banks × 8 bits
Power Supply Voltage VDD: 2.5 V ± 0.15 V
VDDQ: 2.5 V ± 0.15 V
2.5 V CMOS I/O comply with SSTL_2 (half strength driver)
Package:
400 × 875 mil, 66 pin TSOPII, 0.65 mm pin pitch (TSOPII66-P-400-0.65)
Notice: FCRAM is a trademark of Fujitsu Limited, Japan.
www.DataSheet4U.com
www.DataSheet4U.com
Rev 1.2
2005-06-21 1/39

1 page




TC59LM806CFT pdf
TC59LM814/06CFT-50,-60
NOTES:
(1) All voltages referenced to VSS, VSSQ.
(2) VREF is expected to track variations in VDDQ DC level of the transmitting device.
Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
(3) Overshoot limit: VIH (max) = VDDQ + 0.9 V with a pulse width 5 ns.
(4) Undershoot limit: VIL (min) = −0.9 V with a pulse width 5 ns.
(5) VIH (DC) and VIL (DC) are levels to maintain the current logic state.
(6) VIH (AC) and VIL (AC) are levels to change to the new logic state.
(7) VID is magnitude of the difference between CLK input level and CLK input level.
(8) The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device.
(9) VISO means {VICK (CLK) + VICK ( CLK )} /2
(10) Refer to the figure below.
CLK
CLK
VSS
Vx
VICK
|VID (AC)|
Vx
VICK
Vx Vx Vx VID (AC)
VICK
VICK
0 V Differential
VISO
VSS
VISO (min)
VISO (max)
(11) In the case of external termination, VTT (termination voltage) should be gone in the range of VREF (DC)
± 0.04 V.
CAPACITANCE (VDD, VDDQ = 2.5 V, f = 1 MHz, Ta = 25°C)
SYMBOL
PARAMETER
CIN Input pin Capacitance
CINC
Clock pin (CLK, CLK ) Capacitance
CI/O
CNC1
CNC2
I/O pin (DQ, DQS) Capacitance
NC1 pin Capacitance
NC2 pin Capacitance
Note: These parameters are periodically sampled and not 100% tested.
The NC2 pins have additional capacitance for adjustment of the adjacent pin capacitance.
The NC2 pins have Power and Ground clamp.
MIN
2.5
2.5
4.0
4.0
MAX
4.0
4.0
6.0
1.5
6.0
UNIT
pF
pF
pF
pF
pF
Rev 1.2
2005-06-21 5/39

5 Page





TC59LM806CFT arduino
TIMING DIAGRAMS
Input Timing
CLK
CLK
CS
FN
A0~A14
BA0, BA1
tCK
tIS tIH
1st
tIS tIH
1st
tIPW
tIS
tIH
UA, BA
tIPW
tCK
tIS tIH
2nd
tIPW
tIS tIH
2nd
tIS tIH
LA
TC59LM814/06CFT-50,-60
tCH tCL
DQS
DQ (input)
Timing of the CLK, CLK
CLK
CLK
tDS tDH
tDIPW
tCH
tDS tDH
tDIPW
tCL
tT
tCK
Refer to the Command Truth Table.
VIH
VIH (AC)
VIL (AC)
VIL
tT
CLK
VIH
VID (AC)
CLK
VIL
VX VX VX
Rev 1.2
2005-06-21 11/39

11 Page







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