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PDF MC74AC273 Data sheet ( Hoja de datos )

Número de pieza MC74AC273
Descripción OCTAL D FLIP-FLOP
Fabricantes Motorola Semiconductors 
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No Preview Available ! MC74AC273 Hoja de datos, Descripción, Manual

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MC74AC273
MC74ACT273
Octal D FlipĆFlop
The MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered Clock (CP) and Master
Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time
before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-
flop’s Q output.
All outputs will be forced LOW independently of Clock or Data inputs by a LOW
voltage level on the MR input. The device is useful for applications where the true
output only is required and the Clock and Master Reset are common to all storage
elements.
Ideal Buffer for MOS Microprocessor or Memory
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Buffered, Asynchronous Master Reset
See MC74AC377 for Clock Enable Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
Outputs Source/Sink 24 mA
• ′ACT273 Has TTL Compatible Inputs
VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND
PIN NAMES
D0–D7
MR
CP
Q0–Q7
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
OCTAL D FLIP-FLOP
N SUFFIX
CASE 738-03
PLASTIC
DW SUFFIX
CASE 751D-04
PLASTIC
LOGIC SYMBOL
D0 D1 D2 D3 D4 D5 D6 D7
CP
MR
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
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FACT DATA
5-1
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MC74AC273 pdf
MC74AC273 MC74ACT273
DC CHARACTERISTICS
74ACT
74ACT
Symbol
Parameter
VCC
(V)
TA = +25°C
TA =
–40°C to +85°C
Unit
Conditions
Typ Guaranteed Limits
VIH
VIL
VOH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
4.5 1.5 2.0
5.5 1.5 2.0
4.5 1.5 0.8
5.5 1.5 0.8
4.5 4.49 4.4
5.5 5.49 5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
VOUT = 0.1 V
or VCC – 0.1 V
V
VOUT = 0.1 V
or VCC – 0.1 V
V IOUT = –50 µA
VOL
Maximum Low Level
Output Voltage
4.5 3.86
5.5 4.86
4.5 0.001 0.1
5.5 0.001 0.1
3.76
4.76
0.1
0.1
*VIN = VIL or VIH
V
IOH
–24 mA
–24 mA
V IOUT = 50 µA
IIN Maximum Input
Leakage Current
*VIN = VIL or VIH
4.5
5.5
0.36 0.44
0.36 0.44
V
IOL
24 mA
24 mA
5.5
±0.1 ±1.0
µA VI = VCC, GND
ICCT
IOLD
IOHD
ICC
Additional Max. ICC/Input
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5 0.6
5.5
5.5
5.5 8.0
1.5
75
–75
80
mA VI = VCC – 2.1 V
mA VOLD = 1.65 V Max
mA VOHD = 3.85 V Min
µA VIN = VCC or GND
* All outputs loaded; thresholds on input associated with output under test.
† Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (For Figures and Waveforms — See Section 3)
74ACT
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
fmax
Maximum Clock
Frequency
tPHL
Propagation Delay
Clock to Output
tPLH
Propagation Delay
Clock to Output
tPHL
Propagation Delay
MR to Output
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
Min Typ Max
5.0 125 200
5.0 3.0 6.0 10
5.0 3.0 6.5 11
5.0 3.0 7.0 11
74ACT
TA = –40°C
to +85°C
CL = 50 pF
Min Max
125
2.5 11.0
2.5 12.0
2.5 11.5
Unit
MHz
ns
ns
ns
Fig.
No.
3-3
3-6
3-6
3-6
FACT DATA
5-5

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