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PDF MC74AC273 Data sheet ( Hoja de datos )
| Número de pieza | MC74AC273 | |
| Descripción | Octal D Flip-Flop | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74AC273, MC74ACT273
Octal D Flip-Flop
The MC74AC273/74ACT273 has eight edge-triggered D−type
flip−flops with individual D inputs and Q outputs. The common
buffered Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip−flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the LOW−to−HIGH clock transition, is transferred
to the corresponding flip−flop’s Q output.
All outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input. The device is useful
for applications where the true output only is required and the Clock
and Master Reset are common to all storage elements.
Features
• Ideal Buffer for MOS Microprocessor or Memory
• Eight Edge-Triggered D Flip−Flops
• Buffered Common Clock
• Buffered, Asynchronous Master Reset
• See MC74AC377 for Clock Enable Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC374 for 3-State Version
• Outputs Source/Sink 24 mA
• ′ACT273 Has TTL Compatible Inputs
• These are Pb−Free Devices
VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND
(Top View)
Pinout: 20−Lead Packages Conductors
MODE SELECT-FUNCTION TABLE
Operating Mode
Reset (Clear)
Inputs
MR CP
LX
Dn
X
Load ′1′
HH
Load ′0′
HL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Outputs
Qn
L
H
L
www.onsemi.com
20
1
SOIC−20WB
SUFFIX DW
CASE 751D
20
1
TSSOP−20
SUFFIX DT
CASE 948E
PIN ASSIGNMENT
PIN
D0−D7
MR
CP
FUNCTION
Data Inputs
Master Reset
Clock Pulse Input
Q0−Q7
Data Outputs
D0 D1 D2 D3 D4 D5 D6 D7
CP
MR
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
December, 2016 − Rev. 8
1
Publication Order Number:
MC74AC273/D
1 page  
MC74AC273, MC74ACT273
DC CHARACTERISTICS
74ACT
74ACT
Symbol
Parameter
VIH Minimum High Level Input Voltage
VIL Maximum Low Level Input Voltage
VOH Minimum High Level Output Voltage
VCC
(V)
TA = +25°C
TA =
−40°C to +85°C
Typ Guaranteed Limits
4.5 1.5 2.0
5.5 1.5 2.0
2.0
2.0
4.5 1.5 0.8
5.5 1.5 0.8
0.8
0.8
4.5 4.49 4.4
5.5 5.49 5.4
4.4
5.4
4.5 − 3.86
5.5 − 4.86
VOL Maximum Low Level Output Voltage 4.5 0.001 0.1
5.5 0.001 0.1
3.76
4.76
0.1
0.1
4.5 − 0.36
5.5 − 0.36
IIN
DICCT
IOLD
IOHD
Maximum Input Leakage Current
Additional Max. ICC/Input
†Minimum Dynamic Output Current
5.5 − ±0.1
5.5 0.6
−
5.5 −
5.5 −
−
−
ICC Maximum Quiescent Supply Current 5.5 − 8.0
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
0.44
0.44
±1.0
1.5
75
−75
80
Unit Conditions
V
VOUT = 0.1 V
or VCC − 0.1 V
V
VOUT = 0.1 V
or VCC − 0.1 V
V IOUT = −50 mA
*VIN = VIL or VIH
V IOH −24 mA
−24 mA
V IOUT = 50 mA
*VIN = VIL or VIH
V 24 mA
IOL 24 mA
mA VI = VCC, GND
mA VI = VCC − 2.1 V
mA VOLD = 1.65 V Max
VOHD = 3.85 V Min
mA VIN = VCC or GND
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
Symbol
Parameter
fmax Maximum Clock Frequency
tPHL Propagation Delay Clock to Output
tPLH Propagation Delay Clock to Output
tPHL Propagation Delay MR to Output
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
VCC*
(V)
5.0
5.0
5.0
5.0
74ACT
TA = +25°C CL = 50 pF
Min Typ Max
125 200
−
3.0 6.0 10
3.0 6.5 11
3.0 7.0 11
74ACT
TA = −40°C to +85°C
CL = 50 pF
Min Max
125 −
2.5 11.0
2.5 12.0
2.5 11.5
Unit
MHz
ns
ns
ns
Figure
No.
3−3
3−6
3−6
3−6
AC OPERATING REQUIREMENTS
74ACT
74ACT
Symbol
Parameter
ts Setup Time, HIGH or LOW − Data to CP
th Hold Time, HIGH or LOW − Data to CP
tw Clock Pulse Width − HIGH or LOW
tw MR Pulse Width − HIGH or LOW
trec Recovery Time − MR to CP
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
VCC*
(V)
5.0
5.0
5.0
5.0
5.0
TA = +25°C CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Typ Guaranteed Minimum
3.0 4.5
5.0
−2.5 2.0
2.0
2.5 4.0
4.5
2.5 4.0
4.5
−1.0 2.0
3.0
Unit
ns
ns
ns
ns
ns
Figure
No.
3−9
3−9
3−6
3−6
3−6
CAPACITANCE
Symbol
Parameter
CIN Input Capacitance
CPD Power Dissipation Capacitance
Value Typ
4.5
50
Unit
pF
pF
Test Conditions
VCC = 5.0 V
VCC = 5.0 V
www.onsemi.com
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