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PDF GVT7C1361A Data sheet ( Hoja de datos )

Número de pieza GVT7C1361A
Descripción (GVT7xxxx) 256K x 36 / 512K x 18 Sunchronous Burse Flowthrough SRAM
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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( DataSheet : www.DataSheet4U.com )
1CY7C1361A
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM
Features
• Fast access times: 6.0, 6.5, 7.0, and 8.0 ns
• Fast clock speed: 150, 133, 117, and 100 MHz
• 1 ns set-up time and hold time
• Fast OE access times: 3.5 ns and 4.0 ns
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Multiple chip enables for depth expansion:
three chip enables for TA(GVTI)/A(CY) package version
and two chip enables for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package versions
• Address pipeline capability
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• JTAG boundary scan for B and T package version
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The GVT71256B36/CY7C1361A and GVT71512B18/
CY7C1363A SRAMs integrate 262,144x36 and 524,288x18
SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All synchro-
nous inputs are gated by registers controlled by a positive-
edge-triggered Clock Input (CLK). The synchronous inputs in-
clude all addresses, all data inputs, address-pipelining Chip
Enable (CE), depth-expansion Chip Enables (CE2 and CE2),
Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables
(BWa, BWb, BWc, BWd, and BWE), and Global Write (GW).
However, the CE2 chip enable input is only available for TA(GV-
TI)/A(CY) package version.
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-
sions, four pins are used to implement JTAG test capabilities:
Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),
and Test Data-Out (TDO). The JTAG circuitry is used to serially
shift data to and from the device. JTAG inputs use
LVTTL/LVCMOS levels to shift data during this testing mode of
operation. The TA package version does not offer the JTAG
capability.
The GVT71256B36 and GVT71512B18 operate from a +3.3V
power supply. All inputs and outputs are LVTTL compatible.
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
7C1361A-150
7C1363A-150
71256B36-6
71512B18-6
6.0
400
10
7C1361A-133
7C1363A-133
71256B36-6.5
71512B18-6.5
6.5
360
10
7C1361A-117
7C1363A-117
71256B36-7
71512B18-7
7.0
320
10
7C1361A-100
7C1363A-100
71256B36-8
71512B18-8
8.0
270
10
www.DataSheet4U.com
wwwC.yDparteaSssheSete4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 11, 2001

1 page




GVT7C1361A pdf
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
256K x 36 Pin Descriptions
Pin
x36 PBGA Pins x36 QFP Pins Name
Type
Description
4P
37
A0
Input-
Addresses: These inputs are registered and must meet the set-
4N 36 A1 Synchronous up and hold times around the rising edge of CLK. The burst
2A, 3A, 5A, 6A, 35, 34, 33, 32, A
counter generates internal addresses associated with A0 and A1,
3B, 5B, 6B, 2C, 100, 99, 82, 81,
during burst cycle and wait cycle.
3C, 5C, 6C, 2R, 44, 45, 46, 47,
6R, 3T, 4T, 5T
48, 49, 50
92 (A/T version)
43 (AJ/TA ver-
sion)
5L
93
BWa
Input-
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for
5G 94 BWb Synchronous a READ cycle. BWa controls DQa. BWb controls DQb. BWc con-
3G 95 BWc
trols DQc. BWd controls DQd. Data I/O are high impedance if
3L 96 BWd
either of these inputs are LOW, conditioned by BWE being LOW.
4M
87
BWE
Input-
Write Enable: This active LOW input gates byte write operations
Synchronous and must meet the set-up and hold times around the rising edge
of CLK.
4H
88
GW
Input-
Global Write: This active LOW input allows a full 36-bit WRITE to
Synchronous occur independent of the BWE and BWn lines and must meet the
set up and hold times around the rising edge of CLK.
4K
89
CLK
Input-
Clock: This signal registers the addresses, data, chip enables,
Synchronous write control and burst control inputs on its rising edge. All syn-
chronous inputs must meet set up and hold times around the
clock’s rising edge.
4E
98
CE
Input-
Chip Enable: This active LOW input is used to enable the device
Synchronous and to gate ADSP.
2B
97
CE2
Input-
Chip Enable: This active HIGH input is used to enable the device.
Synchronous
(not available for 92 (for AJ/TA
PBGA)
version only)
CE2
Input-
Chip Enable: This active LOW input is used to enable the device.
Synchronous Not available for B and T package versions.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input enables the
data output drivers.
4G
83
ADV
Input-
Address Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
4A
84
ADSP
Input-
Address Status Processor: This active LOW input, along with CE
Synchronous being LOW, causes a new external address to be registered and
a READ cycle is initiated using the new address.
4B
85
ADSC
Input-
Address Status Controller: This active LOW input causes device
Synchronous to be deselected or selected along with new external address to
be registered. A READ or WRITE cycle is initiated depending
upon write control inputs.
3R
31
MODE
Input-
Mode: This input selects the burst sequence. A LOW on this pin
Static
selects linear burst. A NC or HIGH on this pin selects interleaved
burst.
7T
64
ZZ
Input-
Snooze: This active HIGH input puts the device in low power
Asynchro- consumption standby mode. For normal operation, this input has
nous
to be either LOW or NC (No Connect).
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GVT7C1361A arduino
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
TAP Controller Instruction Set
Overview
There are two classes of instructions defined in the IEEE Stan-
dard 1149.1-1990; the standard (public) instructions and de-
vice specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully implemented.
The TAP on this device may be used to monitor all input and
I/O pads, but can not be used to load address, data, or control
signals into the device or to preload the I/O buffers. In other
words, the device will not perform IEEE 1149.1 EXTEST,
INTEST, or the preload portion of the SAMPLE/PRELOAD
command.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the in-
struction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the con-
troller is moved to Update-IR state. The TAP instruction sets
for this device are listed in the following tables.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instruc-
tions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in
Capture-DR mode and places the ID register between the TDI
and TDO pins in Shift-DR mode. The IDCODE instruction is
the default instruction loaded in the instruction upon power-up
and at any time the TAP controller is placed in the test-logic
reset state.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded in the in-
struction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controller’s capture setup plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
Moving the controller to Shift-DR state then places the bound-
ary scan register between the TDI and TDO pins. Because the
PRELOAD portion of the command is not implemented in this
device, moving the controller to the Update-DR state with the
SAMPLE/PRELOAD instruction loaded in the instruction reg-
ister has the same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction reg-
ister and the TAP controller is in the Shift-DR state, the bypass
register is placed between TDI and TDO. This allows the board
level scan path to be shortened to facilitate testing of other
devices in the scan path.
Reserved
Do not use these instructions. They are reserved for future
use.
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