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PDF BGB100 Data sheet ( Hoja de datos )
| Número de pieza | BGB100 | |
| Descripción | 0 dBm TrueBlue radio module | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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DISCRETE SEMICONDUCTORS
DATA SHEET
BGB100
0 dBm TrueBlue radio module
Preliminary specification
2002 Jan 03
1 page  
Philips Semiconductors
0 dBm TrueBlue radio module
Preliminary specification
BGB100
The output stage of the transmit chain active part is balanced, for reduced spurious emissions (EMC). It is connected
through a balun (balanced-to-unbalanced) circuit to the TX/RX switch. This switch is controlled by internal logic circuits
in the active die. The balun circuit has built-in selectivity, to further reduce out-of-band spurious emissions.
Receive mode
Also the receiver functionality is fully integrated. It is a near-zero-IF (1 MHz) architecture with active image rejection. The
sensitive RX input of the active die is a balanced configuration, in order to reduce unwanted (spurious) responses. The
balun structure to convert from unbalanced to balanced signals has built-in selectivity. This suppresses GSM-900
frequencies by more than 40 dB. For better immunity to DCS, DECT, GSM-1800 and W_CDMA signals, an extra
band-pass filter has been included.
The synthesizer PLL may be switched off during demodulation. This reduces the effects that reference frequency
breakthrough may have on receiver sensitivity and adjacent channel selectivity, and also reduces the power
consumption. The demodulator contains an advanced DC offset compensation circuit. This reduces the effects of
frequency mismatch between (remote) transmitter and receiver. These may be caused by differences in reference
frequency, but also by frequency drift during open-loop modulation and demodulation.
Because the VCO is directly modulated by the signal present at the T_GFSK pin, this pin should be connected to a
well-defined and stable DC bias voltage, also when in RX mode. Moreover, this bias voltage should already be present
during the S_EN programming pulse. In this way, the PLL can correct for possible frequency offsets that might otherwise
occur.
The demodulated RF signal is compared against a reference (slicer) value and then output. This reference voltage is
derived from the demodulated output signal itself, by the DC extractor circuit. It operates in three subsequent phases,
controlled by the DCXCTR signal:
• In the first phase, during the preamble and the early part of the Acess Code, a Min/Max detector provides a crude but
fast estimate of the required DC voltage. The DCXCTR line should be low during this phase.
• When the DCXCTR line is pulled high, this crude estimate is used as an initial estimate for an integrator circuit that
provides an accurate estimate of the required DC voltage. This is the second phase. The DC value obtained is derived
from the Barker sequence and the trailer, which together make up the final 10 bits of the Acess Code. The DCXCTR
line should be pulled high 20 µs before the trailer sequence is expected to end (there is a ±10 µs timing uncertainty
between the expected and the actual end of the trailer sequence).
• Exactly at the end of the trailer, the DCXCTR line must be pulled low again. The device now enters the third phase,
during which the estimate of the offset voltage that was obtained during phases one and two is retained. A small and
slow variation to compensate carrier frequency drift can still be tracked.
An RSSI output with a high dynamic range of more than 50 dB provides near-instantaneous information on the quality
of the signal received.
Due to the IF frequency at 1 MHz, in RX mode the VCO frequency should be 1 MHz higher than the channel frequency.
This should be taken care of by the baseband controller.
Power-down mode
In Power-down mode, current consumption is reduced to below 60 µA. The 3-wire bus inputs present a high-ohmic
resistance to ground.
2002 Jan 03
5
5 Page 
Philips Semiconductors
0 dBm TrueBlue radio module
Preliminary specification
BGB100
TIMING DIAGRAMS
S_DATA
S_CLK
S_EN
31 30 29
32 clock cycles
210
t3
3-wire serial bus timing
S_CLK/DATA
REFCLK
S_EN
T_GFSK
R_DATA
DCXCTR
t1
t3 t4
t8
TX packet
t2
t9
RX packet
t1 t2
t5 t7
t3
t4
t10
t11
t12
Fig.3 Timing diagram.
t6 t7
2002 Jan 03
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet BGB100.PDF ] | |
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