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PDF ICM7211A Data sheet ( Hoja de datos )
| Número de pieza | ICM7211A | |
| Descripción | 4-Digit LCD Display Driver | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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ICM7211A
August 2001
4-Digit, LCD Display Driver
Features
Description
• Four Digit Non-Multiplexed 7 Segment LCD Display
Outputs with Backplane Driver
• Complete Onboard RC Oscillator to Generate Backplane
Frequency
• Backplane Input/Output Allows Simple Synchronization
of Slave-Devices to a Master
• ICM7211A Devices Provide Separate Digit Select Inputs
to Accept Multiplexed BCD Input (Pinout and
Functionally Compatible with Siliconix DF411)
• ICM7211AM Devices Provide Data and Digit Address
Latches Controlled by Chip Select Inputs to Provide a
Direct High Speed Processor Interface
• Decodes Binary to Code B (0-9, Dash, E, H, L, P, Blank)
• Available in Surface Mount Package
The ICM7211A (LCD) device constitutes a family of non-mul-
tiplexed four-digit seven-segment CMOS display decoder-
drivers.
The ICM7211A devices are configured to drive conventional
LCD displays by providing a complete RC oscillator, divider
chain, backplane driver, and 28 segment outputs.
This device is available with multiplexed or microprocessor
input configurations. The multiplexed versions provide four
data inputs and four Digit Select inputs. This configuration is
suitable for interfacing with multiplexed BCD or binary output
devices, such as the ICL7135. The microprocessor versions
provide data input latches and Digit Address latches under
control of high-speed Chip Select inputs. These devices sim-
plify the task of implementing a cost-effective alphanumeric
seven-segment display for microprocessor systems, without
requiring extensive ROM or CPU time for decoding and dis-
play updating.
The ICM7211A provides the “Code B” output code, i.e., 0-9,
dash, E, H, L, P, blank, but will correctly decode true BCD to
seven-segment decimal outputs.
Ordering Information
DISPLAY DISPLAY
PART NUMBER TYPE DECODING
INPUT
DISPLAY DRIVE TEMP.
INTERFACING
TYPE
RANGE (oC) PACKAGE
PKG. NO.
ICM7211AlPL
LCD Code B
Multiplexed
Direct Drive
-40× to 85× 40 Ld PDIP
E40.6
ICM7211AMlPL
LCD Code B
Microprocessor
Direct Drive
-40× to 85× 40 Ld PDIP
E40.6
ICM7211AMlM44
LCD Code B
Microprocessor
Direct Drive
-40× to 85× 44 Ld MQFP Q44.10x10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
w1w-8w8.8D-INaTtaESRShIeLeotr43U21.c-7o2m4-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001
1
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File Number 3158.4
1 page  
ICM7211A
Input Definitions In this table, VDD and VSS are considered to be normal operating input logic levels. Actual input low and high levels are
specified under Operating Characteristics. For lowest power consumption, input signals should swing over the full supply.
INPUT
DIP TERMINAL
CONDITIONS
FUNCTION
B0
B1
B2
B3
OSC
27
VDD = Logical One
Ones (Least Significant)
VSS = Logical Zero
28
VDD = Logical One
Twos
VSS = Logical Zero
29
VDD = Logical One
Fours
VSS = Logical Zero
Data Input Bits
30
VDD = Logical One
Eights (Most Significant)
VSS = Logical Zero
36 Floating or with External Oscillator Input
Capacitor to VDD
VSS Disables BP output devices, allowing segments to be synchronized to
an external signal input at the BP terminal (Pin 5).
Multiplexed-Binary Input Configuration
INPUT
TERMINAL
D1 31
D2 32
D3 33
D4 34
CONDITIONS
VDD = Active
VSS = Inactive
FUNCTION
D1 Digit Select (Least Significant)
D2 Digit Select
D3 Digit Select
D4 Digit Select (Most Significant)
Microprocessor Interface Input Configuration
INPUT DESCRIPTION DIP TERMINAL
CONDITIONS
DA1
DA2
Digit Address
Bit 1 (LSB)
Digit Address
Bit 2 (MSB)
31 VDD = Logical One
VSS = Logical Zero
32 VDD = Logical One
VSS = Logical Zero
CS1 Chip Select 1
CS2 Chip Select 2
Timing Diagrams
33 VDD = Inactive
VSS = Active
34 VDD = Inactive
VSS = Active
DIGIT SELECT
DN-1
tIDS
DIGIT SELECT
DN
FUNCTION
DA1 and DA2 serve as a 2-bit Digit Address Input
DA2, DA1 = 00 selects D4
DA2, DA1 = 01 selects D3
DA2, DA1 = 10 selects D2
DA2, DA1 = 11 selects D1
When both CS1 and CS2 are taken low, the data at the Data
and Digit Select code inputs are written into the input latches.
On the rising edge of either Chip Select, the data is decoded
and written into the output latches.
tWH
tIDS
tDH
CS1
(CS2)
CS2
(CS1)
DATA AND
DIGIT
ADDRESS
DATA VALID
DN-1
DATA VALID
DN
tDS
FIGURE 1. MULTIPLEXED INPUT
tWI tICS
tDH
tDS
= DON’T CARE
FIGURE 2. MICROPROCESSOR INTERFACE INPUT
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet ICM7211A.PDF ] | |
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