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PDF GMM2649233ETG Data sheet ( Hoja de datos )

Número de pieza GMM2649233ETG
Descripción 8Mx64 Bits PC100/PC133 Sdram Unbuffered Dimm Based on 8Mx8 Sdram With Lvttl
Fabricantes Hynix Semiconductor 
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8Mx64 bits
PC100/PC133 SDRAM Unbuffered DIMM
based on 8Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
GMM2649233ETG
Description
The GMM2649233ETG is a 8M x 64bits
Synchronous Dynamic RAM MODULE
which is assembled 8 pieces of 8M x 8bits
Synchronous DRAMs in 54 pin TSOP II
package and one 2048 bit EEPROM in 8pin
TSSOP package mounted on a 168 pin
printed circuit board with decoupling
capacitors. The GMM2649233ETG is
optimized for application to the systems which
are required high density and large capacity
such as main memory of the computers and an
image memory systems, and to the others
which are requested compact size.
The GMM2649233ETG provides common
data inputs and outputs.
GMM2649233ETG
(-7K/7J) Single side (-10K) Double side
Features
* PC133/PC100/PC66 Compatible
-7(143MHz)/-75(133MHz)/-8(125MHz)
-7K(PC100,2-2-2),7J(PC100,3-2-2)
* 3.3V +/- 0.3V Power supply
* Maximum Clock frequency
100/125/133/143 MHz
* LVTTL Interface
* Burst read/write operation and burst read/
single write operation capability
* Programmable burst length ;
1, 2, 4, 8, Full page
* Programmable burst sequence
Sequential / Interleave
* Full Page burst length capability
Sequential burst
Burst stop capability
* Programmable CAS Latency ; 2, 3
CKE power down mode
* Input / Output data masking
* 4096 Refresh Cycles / 64ms
* Auto refresh / Self refresh Capability
* Serial Presence Detect with EEPROM
Pin Name
CK0, 1, 2, 3
CKE0
S0, 2
RAS
CAS
WE
A0 ~ A11
BA0,1
DQ0 ~ 63
DQMB0 ~ 7
VCC
VSS
NC
VREF
SDA
SCL
SA0 ~ 2
DU
Clock input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address input
Bank Address input
Data input / output
Data input / output Mask
Power for internal circuit
Ground for internal circuit
No Connect
Power Supply for Reference
Serial Data input/ output
Serial Clock
Address in EEPROM
Don't Use
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/Apr.01
-1-
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GMM2649233ETG pdf
GMM2649233ETG
Pin Description
Pin Name
CK0, 1, 2, 3
(input pins)
DESCRIPTION
CK is the master clock input to this pin. The other input signals are
referred at CK rising edge.
CKE0
(input pin)
S0, 2
(input pins)
RAS, CAS and WE
(input pins)
A0 ~ A11
(input pins)
BA0,1
(input pin)
This pin determines whether or not the next CK is valid. If CKE is
High, the next CK rising edge is valid. If CKE is Low, the next CK
rising edge is invalid. This pin is used for power-down and clock
suspend modes.
When S is Low, the command input cycle becomes valid. When S is
high, all inputs are ignored. However, internal operations (bank active,
burst operations, etc.) are held.
Although these pin names are the same as those of conventional
DRAMs, they function in a different way. These pins define operation
commands (read, write, etc.) depending on the combination of their
voltage levels. For details, refer to the command operation section.
Row address (AX0 to AX11) is determined by A0 to A11 level at the
bank active command cycle CK rising edge. Column address is
determined by A0 to A8 level at the read or write command cycle CK
rising edge. And this column address becomes burst access start
address. A10 defines the precharge mode. When A10 = High at the
precharge command cycle, both banks are precharged. But when A10 =
Low at the precharge command cycle, only the bank that is selected by
BA0 is precharged.
BA0,1 are bank select signal. If BA0 is Low and BA1 is High, bank 0 is
selected. If BA0 is High and BA1 is Low, bank 1 is selected. If BA0 is
Low and BA1 is High, bank 2 is selected. If BA0 is High and BA1 is
High, bank 3 is selected.
DQ0 ~ DQ63
(I/O pins)
Data is input and output from these pins. These pins are the same as
those of a conventional DRAMs.
DQMB0 ~ DQMB7
(input pins)
DQMB controls input/output buffers.
*Read operation: If DQMB is High, The output buffer becomes High-Z.
If the DQMB is Low, the output buffer becomes Low-Z.
*Write operation: If DQMB is High, the previous data is held (the new data
is not written). If DQMB is Low, the data is written.
VCC 3.3 V is applied. (VCC is for the internal circuit)
(power supply pins)
VSS Ground is connected. (VSS is for the internal circuit)
(power supply pins)
NC No Connection pins.
Rev. 1.1/Apr.01
-5-

5 Page





GMM2649233ETG arduino
GMM2649233ETG
Relationship Between Frequency and Minimum Latency
Parameter
-7 -75 -8 -7K -7J
frequency(MHz)
Symbol 143 100 133 100 125 100 100 100 100 66 Notes
tCK (ns)
Active command to column
command (same bank)
Active command to active
command (same bank)
Active command to Precharge
command (same bank)
Precharge command to active
command (same bank)
Write recovery or last data-in to
Precharge command (same bank)
Active command to active
command (different bank)
Self refresh exit time
Last data in to active command
(Auto Precharge, same bank)
Self refresh exit to command
input
Precharge
command to
high impedance
(CL=2)
(CL=3)
Last data out to active
command
(auto Precharge) (same bank)
Last data out to
Precharge
(early Precharge)
(CL=2)
(CL=3)
Column command to column
command
Write command to data in
latency
DQM to data in
lRCD
lRC
lRAS
lRP
lRWL
lRRD
lSREX
lAPW
lSEC
lHZP
lHZP
lAPR
lEP
lEP
lCCD
lWCD
lDID
7 10 7.5 10 8 10 10 10 10 15
323232 2222
1
9
79
7
9
7
7
77
6
= l[ RAS
+lRP], 1
656565 5554 1
323232 2222
1
111111 1111
1
222222 2222
1
111112 1112
4
34
3
4
3
3
33
3
= l[ RWL
+lRP], 1
9 7 9 7 9 7 7 7 7 6 = [lRC]
- 2- 2 - 2 22- 2
333333 3333
111111 1111
- -1 - -1 - -1 - 1 - 1 - -1
-2 -2 -2 -2 -2 -2 - 2 - 2 - 2 - 2
111111 1111
000000 0000
000000 0000
DQM to data out
lDOD 2 2 2 2 2 2 2 2 2 2
CKE to CLK disable
lCLE 1 1 1 1 1 1 1 1 1 1
Register set to active command lRSA 1 1 1 1 1 1 1 1 1 1
CS to command disable
lCDD 0 0 0 0 0 0 0 0 0 0
Power down exit to command
input
lPEC
111111 1111
Rev. 1.1/Apr.01
-11-

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