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PDF DM74LS174 Data sheet ( Hoja de datos )

Número de pieza DM74LS174
Descripción (DM74LS174 / DM74LS175) Hex/Quad D-Type Flip-Flops with Clear
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! DM74LS174 Hoja de datos, Descripción, Manual

August 1992
Revised April 2000
DM74LS174 • DM74LS175
Hex/Quad D-Type Flip-Flops with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input, and the quad (175) versions feature complementary
outputs from each flip-flop.
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a partic-
ular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the HIGH or LOW level, the D input signal has no
effect at the output.
Features
s DM74LS174 contains six flip-flops with single-rail
outputs
s DM74LS175 contains four flip-flops with double-rail
outputs
s Buffered clock and direct clear inputs
s Individual data input to each flip-flop
s Applications include:
Buffer/storage registers
Shift registers
Pattern generators
s Typical clock frequency 40 MHz
s Typical power dissipation per flip-flop 14 mW
Ordering Code:
Order Number Package Number
Package Description
DM74LS174M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS174SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS174N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74LS175M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS175SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS175N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
DM74LS174
DM74LS175
© 2000 Fairchild Semiconductor Corporation DS006404
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DM74LS174 pdf
DM74LS175 Recommended Operating Conditions
Symbol
Parameter
VCC Supply Voltage
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
IOH HIGH Level Output Current
IOL LOW Level Output Current
fCLK Clock Frequency (Note 8)
fCLK Clock Frequency (Note 9)
tW Pulse Width
(Note 10)
tSU Data Setup Time (Note 10)
tH Data Hold Time (Note 10)
tREL Clear Release Time (Note 10)
TA Free Air Operating Temperature
Note 8: CL = 15 pF, RL = 2 k, TA = 25°C and VCC = 5V.
Note 9: CL = 50 pF, RL = 2 k, TA = 25°C and VCC = 5V.
Note 10: TA = 25°C and VCC = 5V.
Clock
Clear
Min
4.75
2
0
0
20
20
20
0
25
0
Nom
5
Max
5.25
0.8
0.4
8
30
25
70
Units
V
V
V
mA
mA
MHz
MHz
ns
ns
ns
ns
°C
DM74LS175 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
Min Max
(Note 11)
Units
VI Input Clamp Voltage
VCC = Min, II = −18 mA
VOH HIGH Level
VCC = Min, IOH = Max
Output Voltage
VIL = Max, VIH = Min
VOL LOW Level
VCC = Min, IOL = Max
Output Voltage
VIL = Max, VIH = Min
IOL = 4 mA, VCC = Min
II Input Current @ Max Input Voltage VCC = Max, VI = 7V
IIH HIGH Level Input Current
VCC = Max, VI = 2.7V
IIL LOW Level
VCC = Max
Input Current
VI = 0.4V
Clock
Clear
Data
1.5
V
2.7 3.4
V
0.35
0.25
0.5
0.4
0.1
20
0.4
0.4
0.36
V
mA
µA
mA
IOS Short Circuit Output Current
ICC Supply Current
Note 11: All typicals are at VCC = 5V, TA = 25°C.
VCC = Max (Note 12)
VCC = Max (Note 13)
20
100
mA
11 18 mA
Note 12: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 13: With all outputs OPEN and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V applied to the clock
input.
DM74LS175 Switching Characteristics
at VCC = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
From (Input)
Symbol
Parameter
To (Output)
fMAX
tPLH
tPHL
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Clock to Q or Q
Clock to Q or Q
Clear to Q
Clear to Q
RL = 2 k
CL = 15 pF
CL = 50 pF
Min Max Min Max
30 25
30 32
30 36
25 29
35 42
Units
MHz
ns
ns
ns
ns
5 www.fairchildsemi.com

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