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PDF STE100P Data sheet ( Hoja de datos )
| Número de pieza | STE100P | |
| Descripción | 10/100 FAST ETHERNET 3.3V TRANSCEIVER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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STE100P
10/100 FAST ETHERNET 3.3V TRANSCEIVER
1 DESCRIPTION
The STE100P, also referred to as STEPHY1, is a
high performance Fast Ethernet physical layer inter-
face for 10Base-T and 100Base-TX applications.
It was designed with advanced CMOS technology to
provide a Media Independent Interface (MII) for easy
attachment to 10/100 Media Access Controllers
(MAC) and a physical media interface for 100Base-
TX of IEEE802.3u and 10Base-T of IEEE802.3.
The STEPHY1 supports both half-duplex and full-du-
plex operation, at 10 and 100 Mbps operation. Its op-
erating mode can be set using auto-negotiation,
parallel detection or manual control. It also allows for
the support of auto-negotiation functions for speed
and duplex detection.
2 FEATURES
2.1 Industry standard
■ IEEE802.3u 100Base-TX and IEEE802.3
10Base-T compliant
Figure 2. Block Diagram
Figure 1. Package
TQFP64 (10x10x1.40mm)
Table 1. Order Codes
Part Number
STE100P
Package
TQFP64
■ Support for IEEE802.3x flow control
■ IEEE802.3u Auto-Negotiation support for
10Base-T and 100Base-TX
■ MII interface
■ Standard CSMA/CD or full duplex operation
supported
■ Industrial temperature compliant
LEDS
LEDS
TX_CLK
TXD[3:0]
TX_ER
TX_EN
MDC
MDIO
100Mb/s
4B/5B
TX Channel
Scrambler
Parallel to
Serial
NRZ To NRZI
Encoder
10Mb/s
NRZ To Manchester
Encoder
Link Pulse
Generator
REGISTERS
Auto
Negotiation
Binary To MLT3
Encoder
10 TX
Filter
Loopback
TRANSMITTER
10/100
TXP
TXN
Clock
Generation
System
Clock
RXD[3:0]
RX_ER
RX_DV
RX_CLK
HW
configuration
pins
HW Config
Power Down
100Mb/s
Descrambler
4B/5B Code Align
RX Channel
Serial to
Parallel
NRZI To NRZ
Decoder
Binary To MLT3
Decoder
Clock Recovery
Adaptive
Equalization
BaseLine
Wander
10Mb/s
NRZ To Manchester
Encoder
Link Pulse
Detector
10 TX Filter
Clock Recovery
SMART
Squelch
RECEIVER
10/100
RXP
RXN
September 2004
Rev. 18
1/31
1 page  
STE100P
Table 2. Pin Description (continued)
Pin No. Name
Type
Description
15 iref
O Reference Resistor connecting pin for reference current, directly connect a 5KΩ
± 1% resistor to Vss.
38 ledr10
I/O LED display for 10Ms/s link status. This pin will be driven on continually when
10Mb/s network operating speed is detected.
The pull-up/pull-down status of this pin is latched into the PR20 bit 7 during
power up/reset.
37 ledtr
LED display for Tx/Rx Activity status. This pin will be driven on at a 10 Hz blinking
frequency when either effective receiving or transmitting is detected.
The status of this pin is latched into the PR20 bit 6 during power up/reset.
36 ledl
I/O LED display for Link Status. Blinks when there is TX or RX activity. This pin will
be driven on continually when a good Link test is detected.
The status of this pin is latched into the PR20 bit 5 during power up/reset.
35 ledc
I/O LED display for Full Duplex or Collision status. This pin will be driven on
continually when a full duplex configuration is detected. This pin will be driven on
at a 20 Hz blinking frequency when a collision status is detected in the half duplex
configuration.
The status of this pin is latched into the PR20 bit 4 during power up/reset.
34 leds
I/O LED display for 100Ms/s link status. This pin will be driven on continually when
100Mb/s network operating speed is detected.
The status of this pin is latched into the PR20 bit 3 during power up/reset.
64 cfg0
I Configuration Control 0.
When A/N is enabled, cfg0 determines operating mode advertisement
capabilities in combination with cfg1 when mf0/ PR0:12 =1. (See Table 2)
When A/N is disabled, cfg1 disables mlt3 and directly affects PR19:0
When cfg0 is Low, mlt3 encoder/decoder is enabled and PR19:1 =0.
When cfg0 is High, mlt3 encoder/decoder is bypassed and PR19:1 = 1.
63 cfg1
I Configuration Control 1.
When A/N is enabled, cfg1 determines operating mode advertisement
capabilities in combination with cfg1 when mf0/ PR0:12 =1. (See Table 2)
When A/N is disabled, CFG1 enables Loopback mode and directly affects PR0
bit 14.
When cfg1 is Low, Loopback mode is disabled and PR0:14 = 0.
When cfg1 is High, Loopback mode is enabled and PR0:14 = 1.
28 reset
I Reset (Active-Low). This input must be held low for a minimum of 1 ms to reset
the STE100P. During Power-up, the STE100P will be reset regardless of the
state of this pin, and this reset will not be complete until after >1ms.
29 rip
O Reset In Progress. This output is used to indicate when the device has
completed power-up/reset and the registers and functions can be accessed.
When rip is High, power-up/reset has been successful and the device can be
used normally
When rip is Low, device reset is not complete.
8, 30,31,
32
nc
nc (No Connection)
26, 33
test,
test_se
Test pins. Should be tied to ground for normal operation
27 pwrdwn
I Power Down. When High, forces STE100P into Power Down mode. This pin is
OR’ed with the Power Down bit (PR0:11). During the Power Down mode, txp/txn
outputs and all LED outputs are 3-stated, and the MII interface is isolated.
5/31
5 Page 
STE100P
Table 5. Register Descriptions (continued)
Bit #
Name
Descriptions
Default Val RW Type
13 RF Remote Fault function.
1: with remote fault function.
0 R/W
12,11
--- Reserved
10 FC Flow Control function Ability.
1 R/W
1:supports PAUSE operation of flow control for full duplex link.
9 T4 100BASE-T4 Ability.
0 RO
Always 0: since STE100P doesn’t have 100BASE-T4 ability.
8 TXF 100Base-TX Full duplex Ability.
1: with 100Base-TX full duplex ability.
1 R/W
7 TXH 100Base-TX Half duplex Ability.
1: with 100Base-TX ability.
1 R/W
6 10F 10Base-T Full duplex Ability.
1: with 10Base-T full duplex ability.
1 R/W
5 10H 10Base-T Half duplex Ability.
1: with 10Base-T ability.
1 R/W
4~0 SF Select field.
00000
RO
PR5- ANLP, Auto-Negotiation Link Partner ability
15 LPNP Link partner Next Page ability.
0: link partner without next page ability.
1: link partner with next page ability.
0 RO
14 LPACK Received Link Partner Acknowledge.
0
0: link code work had not received yet.
1: link partner successfully received STE100P’s Link Code Word.
RO
13 LPRF Link Partner’s Remote fault status.
0: no remote fault detected.
1: remote fault detected.
0 RO
12,11
--- Reserved
0 RO
10 LPFC Link Partner’s Flow control ability.
0: link partner without PAUSE function ability.
1: link partner with PAUSE function full duplex link ability.
0 RO
9 LPT4 Link Partner’s 100BASE-T4 ability.
0: link partner without 100BASE-T4 ability.
1: link partner with 100BASE-T4 ability.
0 RO
8 LPTXF Link Partner’s 100Base-TX Full duplex ability.
0: link partner without 100Base-TX full duplex ability.
1: link partner with 100Base-TX full duplex ability.
0 RO
7 LPTXH Link Partner’s 100Base-TX Half duplex ability.
0: link partner without 100Base-TX.
1: link partner with 100Base-TX ability.
0 RO
6 LP10F Link Partner’s 10Base-T Full Duplex ability.
0: link partner without 10Base-T full duplex ability.
1: link partner with 10Base-T full duplex ability.
0 RO
11/31
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STE100P.PDF ] | |
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