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Número de pieza | TC55V8512J | |
Descripción | (TC55V8512J/FT) 8-Bit CMOS SRAM | |
Fabricantes | Toshiba | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de TC55V8512J (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
No Preview Available ! TC55V8512J/FT-12,-15
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT CMOS STATIC RAM
DESCRIPTION
The TC55V8512J/FT is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 524,288
words by 8 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it
operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode,
and output enable ( OE ) provides fast memory access. This device is well suited to cache memory applications
where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL
compatible. The TC55V8512J/FT is available in plastic 36-pin SOJ and 44-pin TSOP with 400mil width for high
density surface assembly.
FEATURES
• Fast access time (the following are maximum values)
TC55V8512J/FT-12:12 ns
TC55V8512J/FT-15:15 ns
• Low-power dissipation
(the following are maximum values)
Cycle Time 12 15 20 25 ns
Operation (max) 170 140 130 110 mA
Standby:4 mA (both devices)
• Single power supply voltage of 3.3 V ± 0.3 V
• Fully static operation
• All inputs and outputs are LVTTL compatible
• Output buffer control using OE
• Package:
SOJ36-P-400-1.27 (J)
(Weight: 1.35 g typ)
TSOP II44-P-400-0.80 (FT) (Weight: 0.45 g typ)
PIN ASSIGNMENT (TOP VIEW)
36 PIN SOJ
44 PIN TSOP
A17
A3
A2
A1
A0
CE
I/O1
I/O2
VDD
GND
I/O3
I/O4
WE
A16
A15
A14
A13
A18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36 NC
35 A4
34 A5
33 A6
32 A7
31 OE
30 I/O8
29 I/O7
28 GND
27 VDD
26 I/O6
25 I/O5
24 A8
23 A9
22 A10
21 A11
20 A12
19 NU
NC
NC
A17
A3
A2
A1
A0
CE
I/O1
I/O2
VDD
GND
I/O3
I/O4
WE
A16
A15
A14
A13
A18
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 NC
43 NC
42 NC
41 A4
40 A5
39 A6
38 A7
37 OE
36 I/O8
35 I/O7
34 GND
33 VDD
32 I/O6
31 I/O5
30 A8
29 A9
28 A10
27 A11
26 A12
25 NU
24 NC
23 NC
(TC55V8512J)
(TC55V8512FT)
PIN NAMES
A0 to A18 Address Inputs
I/O1 to I/O8 Data Inputs/Outputs
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
VDD
GND
Power (+3.3 V)
Ground
NC No Connection
NU Not Usable (Input)
2001-12-19 1/10
1 page TIMING DIAGRAMS
READ CYCLE (See Note 2)
Address
CE
OE
DOUT
Hi-Z
TC55V8512J/FT-12,-15
tRC
tACC
tCO
tOE
tOH
tCOD (See Note 6)
tOEE (See Note 6)
tCOE (See Note 6)
INDETERMINATE
tODO (See Note 6)
VALID DATA OUT
Hi-Z
INDETERMINATE
WRITE CYCLE 1 ( WE CONTROLLED) (See Note 5)
Address
WE
CE
DOUT
DIN
tWC
tAW
tAS tWP tWR
(See Note 3)
INDETERMINATE
tCW
tODW (See Note 6)
tOEW (See Note 6)
Hi-Z
tDS
tDH
(See Note 4)
INDETERMINATE
VALID DATA IN
2001-12-19 5/10
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet TC55V8512J.PDF ] |
Número de pieza | Descripción | Fabricantes |
TC55V8512FT | (TC55V8512J/FT) 8-Bit CMOS SRAM | Toshiba |
TC55V8512J | (TC55V8512J/FT) 8-Bit CMOS SRAM | Toshiba |
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