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PDF STE400P Data sheet ( Hoja de datos )

Número de pieza STE400P
Descripción 10/100 Fast Ethernet 4 Port Transceiver
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! STE400P Hoja de datos, Descripción, Manual

STE400P
10/100 FAST ETHERNET 4 PORT TRANSCEIVER
1 GENERAL DESCRIPTION
The STE400P, also referred to as STEPHY4, is a
high performance Fast Ethernet physical layer inter-
face for 10BASE-T and 100BASE-TX applications.
It was designed with advanced CMOS technology to
provide a Media Independent Interface (MII) for easy
attachment to 10/100 Media Access Controllers
(MAC) and a physical media interface for 100BASE-
TX of IEEE802.3u and 10BASE-T of IEEE802.3.
The STE400P supports both half-duplex and full-du-
plex operation, at 10 and 100 Mbps operation. Its op-
erating mode can be set using auto-negotiation,
parallel detection or manual control. It also allows for
the support of auto-negotiation functions for speed
and duplex detection.
2 FEATURES
2.1 INDUSTRY STANDARD
s IEEE802.3u 100BASE-TX and IEEE802.3
Figure 1. BLOCK DIAGRAM FOR 1 PORT
PQFP208
ORDERING NUMBER: STE400P
10BASE-T compliant
s Support for IEEE802.3x flow control
s IEEE802.3u Auto-Negotiation support for
10BASE-T and 100BASE-TX
s MII interface
s Standard CSMA/CD or full duplex supported
LEDS
LEDS
TX_CLK
TXD[3:0]
TX_ER
TX_EN
MDC
MDIO
100Mb/s
4B/5B
TX Channel
Scrambler
Parallel to
Serial
NRZ To NRZI
Encoder
10Mb/s
NRZ To Manchester
Encoder
Link Pulse
Generator
REGISTERS
Auto
Negotiation
Binary To MLT3
Encoder
10 TX
Filter
Loopback
TRANSMITTER
10/100
TXP
TXN
Clock
Generation
System
Clock
RXD[3:0]
RX_ER
RX_DV
RX_CLK
COL
CRS
HW
configuration
pins
HW Config
Power Down
100Mb/s
Descrambler
4B/5B Code Align
RX Channel
Serial to
Parallel
NRZI To NRZ
Decoder
Binary To MLT3
Decoder
Clock Recovery
Adaptive
Equalization
BaseLine
Wander
10Mb/s
NRZ To Manchester
Encoder
Link Pulse
Detector
10 TX Filter
Clock Recovery
SMART
Squelch
RECEIVER
10/100
RXP
RXN
November 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
Version: A11
www.DataSheet4U.com
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STE400P pdf
STE400P
Table 1. Pin Description
Pin. Name
Type
Description
MII Interface
33 TXD3 {1}
34 TXD2 {1}
35 TXD1 {1}
36 TXD0 {1}
208 TXD3 {2}
1 TXD2 {2}
9 TXD1 {2}
10 TXD0 {2}
150 TXD3 {3}
149 TXD2 {3}
148 TXD1 {3}
147 TXD0 {3}
124 TXD3 {4}
123 TXD2 {4}
122 TXD1 {4}
121 TXD0 {4}
Ipd Transmit Data. The Media Access Controller (MAC) drives data to the
STE400P using these inputs.
These signals must be synchronized to the TX-CLK.
37 TXEN1
11 TXEN2
146 TXEN3
120 TXEN4
Ipd Transmit Enable. The MAC asserts this signal when it drives valid data on
the TXD inputs. This signal must be synchronized to the TX-CLK.
27 TXC1
12 TXC2
145 TXC3
130 TXC4
O3s Transmit Clock. Normally the STE400P drives TX-CLK. Refer to the Clock
Requirements discussion in the Functional Description section.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
19 RXD3 {1}
20 RXD2 {1}
21 RXD1 {1}
23 RXD0 {1}
192 RXD3 {2}
193 RXD2 {2}
194 RXD1 {2}
195 RXD0 {2}
170 RXD3 {3}
169 RXD2 {3}
168 RXD1 {3}
167 RXD0 {3}
138 RXD3 {4}
137 RXD2 {4}
136 RXD1 {4}
134 RXD0 {4}
O3s Receive Data. The STE400P drives received data on these outputs,
synchronous to RX-CLK.
RXD4 is driven only in Symbol (5B) Mode.
24 RXDV1
196 RXDV2
166 RXDV3
133 RXDV4
O3s Receive Data Valid. The STE400P asserts This signal when it drives valid
data on RXD. This output is synchronous to RX-CLK.
18 RXER1
191 RXER2
171 RXER3
139 RXER4
O3s Receive Error. The STE400P asserts this output when it receives invalid
symbols from the network. This signal is synchronous to RX-CLK. In Symbol
(5B) Mode this pin is also equivalent to RXD4.
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STE400P arduino
STE400P
There are 20 registers with 16 bits each supported for each port of the STE400P. This includes 9 basic registers
which are defined according to the clause 22 “Reconciliation Sub-layer and Media Independent Interface” and
clause 28 “Physical Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair” of
IEEE802.3u standard. In addition, there are 11 registers for advanced chip control and status information.
6.1 MII MANAGEMENT INTERFACE
The STE400P is fully compliant with the IEEE 802.3u MII specifications.
6.2 REGISTER LIST
Table 2. Register List
Address Reg. Index
Name
Register Descriptions
00h PR0 Control MII Control Register
01h PR1 Status MII Status Register
02h PR2 PID HI PHY Identifier (HI) Register
03h PR3 PID LO PHY Identifier (LO) Register
04h
PR4
ANA
Auto-Negotiation Advertisement Register
05h PR5 ANLPA Auto-Negotiation Link Partner Ability Register
06h
RP6
ANE
Auto-Negotiation Expansion Register
07h PR7 NEXT PAGE Auto-Negotiation Next Page Transmit Register
08h PR8 LP NXT PG Auto-Negotiation Link Partner Next Page Transmit Register
10h PR9 100AUXCTL 100BaseX Auxiliary Control Register
11h
PR10
100AUX SR 100BaseX Auxiliary Status Register
12h
PR11
100 RX EC 100BaseX Receiver Error Counter
13h
PR12
100 FCSC 100BaseX False Carrier Sense Counter
18h
PR13
AUX CSR Auxiliary Control/Status Register
19h
PR14
AUX SSR AuxiliaryStatus Summary Register
1Ah
PR15
INT Interrupt Register
1Bh
PR16
AUX M2 Auxiliary Mode 2 Register
1Ch
PR17
AUX EGSR Auxiliary Error and General Status Register
1Dh
PR18
AUX MODE Auxiliary Mode Register
1Eh
PR19
AUX MPR Auxiliary Multiple PHY Register
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