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PDF EP2S60F672C3 Data sheet ( Hoja de datos )

Número de pieza EP2S60F672C3
Descripción (EP2Sxxx) Stratix II Device Family
Fabricantes Altera 
Logotipo Altera Logotipo



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Section I. Stratix II Device
Family Data Sheet
This section provides designers with the data sheet specifications for
Stratix® II devices. They contain feature definitions of the internal
architecture, configuration and JTAG boundary-scan testing information,
DC operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix II devices.
This section contains the following chapters:
Chapter 1. Introduction
Chapter 2. Stratix II Architecture
Chapter 3. Configuration & Testing
Chapter 4. Hot Socketing, ESD & Power-On Reset
Chapter 5. DC & Switching Characteristics
Chapter 6. Reference & Ordering Information
Revision History The table below shows the revision history for Chapters 1 through 6.
Chapter Date / Version
Changes Made
1 March 2005, 2.1 Updated “Introduction” and “Features” sections.
January 2005, v2.0 Added note to Table 1–2.
October 2004, v1.2 Updated Tables 1–2, 1–3, and 1–4.
July 2004, v1.1
Updated Tables 1–1 and 1–2.
Updated “Features” section.
www.DataSheet4U.comFebruary 2004, v1.0 Added document to the Stratix II Device Handbook.
Altera Corporation
www.DataSheet4U.com
Section I–1
Preliminary

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EP2S60F672C3 pdf
1. Introduction
SII51001-2.1
Introduction
Features
Altera Corporation
March 2005
The Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper
SRAM process and features a new logic structure that maximizes
performance, and enables device densities approaching 180,000
equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of
on-chip, TriMatrix™ memory for demanding, memory intensive
applications and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit)
multipliers for efficient implementation of high performance filters and
other DSP functions. Various high-speed external memory interfaces are
supported, including double data rate (DDR) SDRAM and DDR2
SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data
rate (SDR) SDRAM. Stratix II devices support various I/O standards
along with support for 1-gigabit per second (Gbps) source synchronous
signaling with DPA circuitry. Stratix II devices offer a complete clock
management solution with internal clock frequency of up to 550 MHz
and up to 12 phase-locked loops (PLLs). Stratix II devices are also the
industry’s first FPGAs with the ability to decrypt a configuration
bitstream using the Advanced Encryption Standard (AES) algorithm to
protect designs.
The Stratix II family offers the following features:
15,600 to 179,400 equivalent LEs; see Table 1–1
New and innovative adaptive logic module (ALM), the basic
building block of the Stratix II architecture, maximizes performance
and resource usage efficiency
Up to 9,383,040 RAM bits (1,172,880 bytes) available without
reducing logic resources
TriMatrix memory consisting of three RAM block sizes to implement
true dual-port memory and first-in first-out (FIFO) buffers
High-speed DSP blocks provide dedicated implementation of
multipliers (at up to 450 MHz), multiply-accumulate functions, and
finite impulse response (FIR) filters
Up to 16 global clocks with 24 clocking resources per device region
Clock control block supports dynamic clock network enable/disable,
which allows clock networks to power down to reduce power
consumption in user mode
Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device
provide spread spectrum, programmable bandwidth, clock switch-
over, real-time PLL reconfiguration, and advanced multiplication
and phase shifting
1–1

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EP2S60F672C3 arduino
Stratix II Architecture
The number of M512 RAM, M4K RAM, and DSP blocks varies by device
along with row and column numbers and M-RAM blocks. Table 2–1 lists
the resources available in Stratix II devices.
Table 2–1. Stratix II Device Resources
Device
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
M512 RAM
Columns/Blocks
4 / 104
6 / 202
7 / 329
8 / 488
9 / 699
11 / 930
M4K RAM
Columns/Blocks
3 / 78
4 / 144
5 / 255
6 / 408
7 / 609
8 / 768
M-RAM
Blocks
0
1
2
4
6
9
DSP Block
Columns/Blocks
2 / 12
2 / 16
3 / 36
3 / 48
3 / 63
4 / 96
LAB
Columns
LAB Rows
30 26
49 36
62 51
71 68
81 87
100 96
Logic Array
Blocks
Each LAB consists of eight ALMs, carry chains, shared arithmetic chains,
LAB control signals, local interconnect, and register chain connection
lines. The local interconnect transfers signals between ALMs in the same
LAB. Register chain connections transfer the output of an ALM register to
the adjacent ALM register in an LAB. The Quartus® II Compiler places
associated logic in an LAB or adjacent LABs, allowing the use of local,
shared arithmetic chain, and register chain connections for performance
and area efficiency. Figure 2–2 shows the Stratix II LAB structure.
Altera Corporation
March 2005
2–3
Stratix II Device Handbook, Volume 1

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