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PDF KMM366F808CS1 Data sheet ( Hoja de datos )

Número de pieza KMM366F808CS1
Descripción (KMM366F804(8)CS1) DRAM Module
Fabricantes Samsung Semiconductor 
Logotipo Samsung Semiconductor Logotipo



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DRAM MODULE
KMM366F80(8)4CS1
KMM366F80(8)4CS1 EDO Mode without buffer
8M x 64 DRAM DIMM Using 4Mx16, 8K & 4K Refresh, 3.3V
GENERAL DESCRIPTION
The Samsung KMM366F80(8)4CS1 is a 8Mx64bits Dynamic
RAM high density memory module. The Samsung
KMM366F80(8)4CS1 consists of eight CMOS 4Mx16bits
DRAMs in TSOP 400mil packages and one 2K EEPROM for
SPD in 8-pin TSSOP package mounted on a 168-pin glass-
epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is
mounted on the printed circuit board for each DRAM. The
KMM366F80(8)4CS1 is a Dual In-line Memory Module and is
intended for mounting into 168 pin edge connector sockets.
PERFORMANCE RANGE
Speed
-5
tRAC
50ns
tCAC
13ns
-6
60ns
15ns
tRC
84ns
104ns
tHPC
20ns
25ns
FEATURES
• Part Identification
Part number
PKG Ref. CBR Ref. ROR Ref.
KMM366F804CS1 TSOP 4K
4K/64ms
KMM366F884CS1 TSOP 8K 4K/64ms 8K/64ms
• New JEDEC standard proposal without buffer
• Serial Presence Detect with EEPROM
• Extended Data Out Mode Operation
• CAS-before-RAS Refresh capability
• RAS-only and Hidden refresh capability
• LVTTL compatible inputs and outputs
• Single +3.3V±0.3V power supply
• PCB : Height(1000mil), double sided component
PIN CONFIGURATIONS
PIN NAMES
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
Pin Name
Function
1 VSS 29 CAS1 57 DQ18 85 VSS 113 CAS5 141 DQ50
2 DQ0 30 RAS0 58 DQ19 86 DQ32 114 RAS1 142 DQ51
A0 - A11
A0 - A12
Address Input (4K ref.)
Address Input (8K ref.)
3 DQ1 31 OE0 59 VCC 87 DQ33 115 DU 143 VCC
DQ0 - DQ63
Data In/Out
4 DQ2 32 VSS 60 DQ20 88 DQ34 116 VSS 144 DQ52
5 DQ3 33 A0 61 NC 89 DQ35 117 A1 145 NC
6 VCC 34 A2 62 DU 90 VCC 118 A3 146 DU
7 DQ4 35 A4 63 NC 91 DQ36 119 A5 147 NC
W0, W2
OE0, OE2
RAS0 - RAS3
Read/Write Enable
Output Enable
Row Address Strobe
8 DQ5 36 A6 64 VSS 92 DQ37 120 A7 148 VSS
CAS0 - CAS7
Column Address Strobe
9 DQ6 37 A8 65 DQ21 93 DQ38 121 A9 149 DQ53
10 DQ7 38 A10 66 DQ22 94 DQ39 122 A11 150 DQ54
11 DQ8 39 A12 67 DQ23 95 DQ40 123 *A13 151 DQ55
VCC
VSS
Power(+3.3V)
Ground
12 VSS 40 VCC 68 VSS 96 VSS 124 VCC 152 VSS
NC
No Connection
13 DQ9 41 VCC 69 DQ24 97 DQ41 125 DU 153 DQ56
14 DQ10 42 DU 70 DQ25 98 DQ42 126 DU 154 DQ57
15 DQ11 43 VSS 71 DQ26 99 DQ43 127 VSS 155 DQ58
16 DQ12 44 OE2 72 DQ27 100 DQ44 128 DU 156 DQ59
DU
SDA
SCL
Dont use
Serial Address /Data I/O
Serial Clock
17 DQ13 45 RAS2 73 VCC 101 DQ45 129 RAS3 157 VCC
SA0 -SA2
Address in EEPROM
18 VCC 46 CAS2 74 DQ28 102 VCC 130 CAS6 158 DQ60
19 DQ14 47 CAS3 75 DQ29 103 DQ46 131 CAS7 159 DQ61
20 DQ15 48 W2 76 DQ30 104 DQ47 132 DU 160 DQ62
*CB0 - CB7
Check Bit
* These pins are not used in this module.
21 *CB0 49 VCC 77 DQ31 105 *CB4 133 VCC 161 DQ63
22 *CB1 50 NC 78 VSS 106 *CB5 134 NC 162 VSS
23 VSS 51 NC 79 NC 107 VSS 135 NC 163 NC
24 NC 52 *CB2 80 NC 108 NC 136 *CB6 164 NC
25 NC 53 *CB3 81 NC 109 NC 137 *CB7 165 SA0
www.DataSheet4U.com26 VCC 54 VSS 82 SDA 110 VCC 138 VSS 166 SA1
27 W0 55 DQ16 83 SCL 111 DU 139 DQ48 167 SA2
28 CAS0 56 DQ17 84 VCC 112 CAS4 140 DQ49 168 VCC
Note : A12 is used for only KMM366F884CS1 (8K ref.)
www.DataSheet4U.com

1 page




KMM366F808CS1 pdf
DRAM MODULE
KMM366F80(8)4CS1
AC CHARACTERISTICS (0°CTA70°C, VCC=3.3V±0.3V. See notes 1,2.)
Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF
Parameter
Column address to W delay time
CAS precharge to W delay time
CAS setup time (CAS-before-RAS refresh)
CAS hold time (CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Hyper page mode cycle time
Hyper page mode read-modify write cycle time
CAS precharge time (Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
OE access time
OE to data delay
Output buffer turn off delay time from OE
OE command hold time
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
OE to CAS hold time
CAS hold time to OE
OE precharge time
W pulse width (Hyper page cycle)
Symbol
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPA
tHPC
tHPRWC
tCP
tRASP
tRHCP
tOEA
tOED
tOEZ
tOEH
tDOH
tREZ
tWEZ
tWED
tOCH
tCHO
tOEP
tWPE
-5
Min Max
45
47
5
10
5
28
20
67
7
50 200K
30
13
10
3 13
5
5
3 13
3 13
15
5
5
5
5
-6
Min Max
53
58
5
10
5
35
25
73
10
60 200K
35
15
13
3 13
5
5
3 13
3 13
15
5
5
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
7
17
3
10
10
14
6
6,12
6

5 Page





KMM366F808CS1 arduino
DRAM MODULE
HYPER PAGE READ CYCLE
KMM366F80(8)4CS1
VIH -
RAS
VIL -
VIH -
CAS
VIL -
VIH -
A
VIL -
tRASP
tCRP
tCSH
tRCD
tHPC
tCP
tCAS
¡ó
tHPC
tCAS
tCP
tHPC
tCP
tCAS
tRHCP
tCAS
tRAD
tASR tRAH tASC tCAH tASC tCAH tASC tCAH tASC tCAH
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
ADDRESS
tRP
tREZ
VIH -
W
VIL -
VIH -
OE
VIL -
VOH -
DQ
VOL -
tRCS
tCAC
tAA
tCPA
tAA tCAC
tOEA
tRAC
tCAC
tDOH
VALID
DATA-OUT
tOLZ
tCLZ
VALID
DATA-OUT
tCAC
tAA
tCPA
tOCH
tOEA
tRCH
tRRH
tCPA
tCAC
tAA
tCHO
tOEP
tOEP
tOEZ
tOEZ
tOEA
VALID
DATA-OUT
tOEZ
VALID
DATA-OUT
Dont care
Undefined

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