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PDF M5M5W816TP-85HI Data sheet ( Hoja de datos )

Número de pieza M5M5W816TP-85HI
Descripción (M5M5W816TP-55HI/70HI/85HI) CMOS STATIC RAM
Fabricantes Mitsubishi Electric Semiconductor 
Logotipo Mitsubishi Electric Semiconductor Logotipo



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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003

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M5M5W816TP-85HI pdf
2002.08.30 Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Vcc=2.7 ~ 3.6V, unless otherwise noted)
(1) TEST CONDITIONS
Supply v oltage
2.7~3.6V
Input pulse
VIH=2.4V, VIL=0.4V
Input rise time and f all time 5ns
Ref erence lev el
V OH=V OL= 1 . 5 0 V
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
DQ
Output loads
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
1TTL
CL
Including scope and
jig capacitance
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
t CR
ta(A)
ta(S)
ta(BC1)
ta(BC2)
ta(OE)
tdis(S)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S)
ten(BC1,2)
ten(OE)
tV(A)
Read cy cle time
Address access time
Chip select 1 access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time af t er S# high
Output disable time af t er BC1# high
Output disable time af t er BC2# high
Output disable time af t er OE# high
Output enable time af ter S# low
Output enable time af ter BC1#,BC2# low
Output enable time af ter OE# low
Data v alid time after address
55HI
Min Max
55
55
55
55
55
30
20
20
20
20
10
5
5
10
Limits
70HI
Min Max
70
70
70
70
70
35
25
25
25
25
10
5
5
10
85HI
Min Max
85
85
85
85
85
45
30
30
30
30
10
5
5
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Symbol
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(BC1)
tsu(BC2)
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Parameter
Write cy cle time
Write pulse width
Address setup time
Address setup time with respect to W#
By te control 1 setup time
By te control 2 setup time
Chip select setup time
Data setup time
Data hold time
Write recov ery time
Output disable time f rom W# low
Output disable time f rom OE# high
Output enable time f rom W# high
Output enable time f rom OE# low
55HI
Min Max
55
45
0
50
50
50
50
30
0
0
20
20
5
5
Limits
70HI
Min Max
70
55
0
65
65
65
65
35
0
0
25
25
5
5
85HI
Min Max
85
60
0
70
70
70
70
45
0
0
30
30
5
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4

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