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PDF GE28F256K18 Data sheet ( Hoja de datos )

Número de pieza GE28F256K18
Descripción (GE28FxxxKx) Intel StrataFlash Memory (J3)
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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No Preview Available ! GE28F256K18 Hoja de datos, Descripción, Manual

Intel StrataFlash® Synchronous Memory
(K3/K18)
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3,
28F256K18 (x16)
Datasheet
Product Features
Performance
m—110/115/120 ns Initial Access Speed for
64/128/256 Mbit Densities
o—25 ns Asynchronous Page-Mode Reads,
8 Words Wide
.c—13 ns Synchronous Burst-Mode Reads,
8 or 16 Words Wide
— 32-Word Write Buffer
U—Buffered Enhanced Factory
Programming
t4Software
— 25 µs (typ.) Program and Erase Suspend
eLatency Time
— Flash Data Integrator (FDI), Common
eFlash Interface (CFI) Compatible
— Programmable WAIT Signal Polarity
hQuality and Reliability
— Operating Temperature:
S–40 °C to +85 °C
— 100K Minimum Erase Cycles per Block
ata—0.18 µm ETOX™ VII Process
Architecture
— Multi-Level Cell Technology: High
Density at Low Cost
— Symmetrical 64 K-Word Blocks
— 256 Mbit (256 Blocks)
— 128 Mbit (128 Blocks)
— 64 Mbit (64 Blocks)
— Ideal for “CODE + DATA” applications
Security
— 2-Kbit Protection Register
— Unique 64-bit Device Identifier
— Absolute Data Protection with VPEN and
WP#
— Individual and Instantaneous Block
Locking, Unlocking and Lock-Down
Capability
Packaging and Voltage
— 64-Ball Intel® Easy BGA Package
(128-Mbit is also offered in a lead-free
package)
— 56-and 79-Ball Intel® VF BGA Package
— VCC = 2.70 V to 3.60 V
— VCCQ = 1.65 to 1.95 V/2.375 to 3.60 V
The Intel StrataFlash® Synchronous Memory (K3/K18) product line adds a high performance
.Dburst-mode interface and other additional features to the Intel StrataFlash® memory family of
products. Just like its J3 counterpart, the K3/K18 device utilizes reliable and proven two-bit-per-
cell technology to deliver 2x the memory in 1x the space, offering high density flash at low cost.
wThis is Intel’s third generation MLC technology, manufactured on 0.18 µm lithography, making
it the most widely used and proven MLC product family on the market.
wK3/K18 is a 3-volt device (core), but it is available with 3-volt (K3) or 1.8-volt (K18) I/O
mvoltages. These devices are ideal for mainstream applications requiring large storage space for
w oboth code and data storage. Advanced system designs will benefit from the high performance
.cpage and burst modes for direct execution from the flash memory. Available in densities from 64
Mbit to 256 Mbit (32 Mbyte), the K3/K18 device is the highest density NOR-based flash
t4Ucomponent available today, just as it was when Intel introduced the original device in 1997.
heeNotice: This document contains information on new products in production. The specifications
Sare subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
.DataOrder Number: 290737-009
www February 2005

1 page




GE28F256K18 pdf
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
14.3 Read Query/CFI ..................................................................................................58
14.4 STS Configuration (Easy BGA package ONLY)..................................................58
Appendix A Write State Machine (WSM).............................................................................. 59
Appendix B Common Flash Interface ................................................................................... 64
Appendix C Flowcharts............................................................................................................... 70
Appendix D Additional Information ....................................................................................... 78
Appendix E Ordering Information .......................................................................................... 79
Datasheet
5

5 Page





GE28F256K18 arduino
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
2.5 K3/K18 Block Diagram
Figure 1. K3/K18 Device Memory Block Diagram
VCCQ
WAIT
AMAX : AMIN
CLK
ADV#
Input
Buffer
Address
Latch
Address
Counter
Read State
Machine
Y-Decoder
X-Decoder
DQ0 - DQ15
VCCQ
Output
Buffer
Input
Buffer
Query
Identifier
Register
Status
Register
Data
Comparator
Command
User
Interface
Input Multiplexer
I/O Logic
VCCQ
CE#
W E#
OE#
RST#
Y-Gating
64-Mbit: Sixty-four
128-Mbit: One-hundred
twenty-eight
256-Mbit Two-hundred
fifty-six
64Kword Blocks
Write State
Machine
Program/Erase
Voltage Switch
STS
VPEN
VCC
GND
Datasheet
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