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PDF 28F320W18 Data sheet ( Hoja de datos )

Número de pieza 28F320W18
Descripción (28FxxxW18) 1.8 V Wireless Flash Memory
Fabricantes Intel 
Logotipo Intel Logotipo



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1.8 Volt Intel® Wireless Flash Memory
(W18)
28F320W18, 28F640W18, 28F128W18
Preliminary Datasheet
Product Features
s Performance
70 ns Asynchronous reads for 32 and 64 Mbit,
90 ns for 128 Mbit
m14 ns Clock to Data Output (tCHQV)
20 ns Page Mode Read Speed
o4-Word, 8-Word, and Continuous-Word Burst
Modes
.cBurst and Page Modes in Parameter and Main
Partitions
Programmable WAIT Configuration
Enhanced Factory Programming Mode@
U3.50 µs/Word (Typ)
Glueless 12 V interface for Fast Factory
t4Programming @ 8 µs/Word (Typ)
1.8 V Low-Power Programming @ 12 µs/Word
(Typ)
eProgram or Erase during Reads
s Architecture
eMultiple 4-Mbit Partitions
Dual-Operation: Read-While-Write or Read-
hWhile-Erase
Eight, 4-Kword Parameter Code and Data
Blocks
S32-Kword Main Code and Data Blocks
Top and Bottom Parameter Configurations
tas Power Operation
1.7 V to 1.95 V Read and Write Operations
1.7 V to 2.24 V VCCQ for I/O Isolation
aStandby Current: 5 µA (Typ)
Read Current: 7 mA (Typ)
s Software
5 µs (Typ) Program Suspend
5 µs (Typ) Erase Suspend
Intel® Flash Data Integrator (FDI) Software
Optimized
Intel Basic Command Set Compatible
Common Flash Interface (CFI)
s Quality and Reliability
Extended Temperature: 40 °C to +85 °C
Minimum 100,000 Erase Cycles per Block
ETOXVII Flash Technology (0.18 µm)
s Security
128-bit Protection Register: 64 Unique Device
Identifier Bits; 64 User-Programmable OTP
Bits
Absolute Write Protection VPP = GND
Erase/Program Lockout during Power
Transitions
Individual Dynamic Zero-Latency Block
Locking
Individual Block Lock-Down
s Density and Packaging
32 Mbit and 128 Mbit in a VF BGA Package
64 Mbit in a µBGA*Package
56 Active Ball Matrix, 0.75 mm Ball-Pitch
µBGA* and VF BGA Packages
16-bit wide Data Bus
.DThe 1.8 Volt Intel® Wireless Flash memory with flexible multi-partition dual-operation provides high-
performance asynchronous and synchronous burst reads. It is an ideal memory for low-voltage burst CPUs.
wCombining high read performance with flash memorys intrinsic non-volatility, 1.8 Volt Intel Wireless Flash
memory eliminates the traditional system-performance paradigm of shadowing redundant code memory from
slow nonvolatile storage to faster execution memory. It reduces the total memory requirement that increases
wreliability and reduces overall system power consumption and cost.
mThe 1.8 Volt Intel Wireless Flash memorys flexible multi-partition architecture allows programming or erasing to
woccur in one partition while reading from another partition. This allows for higher data write throughput
ocompared to single partition architectures. The dual-operation architecture also allows two processors to
.cinterleave code operations while program and erase operations take place in the background. The designer can
also choose the size of the code and data partitions via the flexible multi-partition architecture.
t4UThe 1.8 Volt Intel Wireless Flash memory is manufactured on Intels 0.18 µm ETOXVII process technology. It
is available in µBGA and VF BGA packages which are ideal for board-constrained applications.
SheeNotice: This document contains preliminary information on new products in production. The
taspecifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
.Da 290701-003
www June 2001

1 page




28F320W18 pdf
1.8 Volt Intel® Wireless Flash Memory (W18)
Revision History
Date of
Revision
09/13/00
01/29/01
06/12/01
Version
Description
290701-001
290701-002
290701-003
Original Version
Deleted 16-Mbit density
Revised ADV#, Section 2.2
Revised Protection Registers, Section 4.16
Revised Program Protection Register, Section 4.18
Revised Example in First Access Latency Count, Section 5.0.2
Revised Figure 5, Data Output with LC Setting at Code 3
Added WAIT Signal Function, Section 5.0.3
Revised WAIT Signal Polarity, Section 5.0.4
Revised Data Output Configuration, Section 5.0.5
Added Figure 7, Data Output Configuration with WAIT Signal Delay
Revised WAIT Delay Configuration, Section 5.0.6
Changed VCCQ Spec from 1.7 V 1.95 V to 1.7 V 2.24 V in Section 8.2,
Extended Temperature Operation
Changed ICCS Spec from 15 µA to 18 µA in Section 8.4, DC
Characteristics
Changed ICCR Spec from 10 mA (CLK = 40 MHz, burst length = 4) and 13
mA (CLK = 52 MHz, burst length = 4) to 13 mA, and 16 mA respectively in
Section 8.4, DC Characteristics
Changed ICCWS Spec from 15 µA to 18 µA in Section 8.4, DC
Characteristics
Changed ICCES Spec from 15 µA to 18 µA in Section 8.4, DC
Characteristics
Changed tCHQX Spec from 5ns to 3ns in Section 8.6, AC Read
Characteristics
Added Figure 25, WAIT Signal in Synchronous Non-Read Array Operation
Waveform
Added Figure 26, WAIT Signal in Asynchronous Page Mode Read
Operation Waveform
Added Figure 27, WAIT Signal in Asynchronous Single Word Read
Operation Waveform
Revised Appendix E, Ordering Information
Revised entire Section 4.10, Enhanced Factory Program Command (EFP)
and Figure 6, Enhanced Factory Program Flowchart
Revised Section 4.13, Protection Register
Revised Section 4.15, Program Protection Register
Revised Section 7.3, Capacitance, to include 128-Mbit specs
Revised Section 7.4, DC Characteristics, to include 128-Mbit specs
Revised Section 7.6, AC Read Characteristics, to include 128-Mbit device
specifications
Added tVHGL Spec in Section 7.6, AC Read Characteristics
Revised Section 7.7, AC Write Characteristics, to include 128-Mbit device
specifications
Minor text edits
v

5 Page





28F320W18 arduino
1.8 Volt Intel® Wireless Flash Memory (W18)
Table 1. Signal Descriptions
Symbol
A[22:0]
DQ[15:0]
ADV#
CE#
CLK
OE#
RST#
WAIT
WE#
WP#
VPP
VCC
VCCQ
VSS
VSSQ
DU
NC
Type
I
I/O
I
I
I
I
I
O
I
I
Pwr/I
Pwr
Pwr
Pwr
Pwr
Name and Function
ADDRESS INPUTS: for memory addresses.
32 Mbit: A[20:0]; 64 Mbit: A[21:0]; 128 Mbit: A[22:0]
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles, outputs data during memory,
status register, protection register, and configuration code reads. Data pins float when the chip or
outputs are deselected. Data is internally latched during writes.
ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous
read operations, all addresses are latched on ADV#s rising edge or CLKs rising (or falling) edge,
whichever occurs first.
CHIP ENABLE: CE#-low activates internal control logic, I/O buffers, decoders, and sense amps. CE#-
high deselects the device, places it in standby state, and places data and WAIT outputs at High-Z.
CLOCK: CLK synchronizes the device to the system bus frequency in synchronous-read configuration
and increments an internal burst address generator. During synchronous read operations, addresses
are latched on ADV#s rising edge or CLKs rising (or falling) edge, whichever occurs first.
OUTPUT ENABLE: Active low OE# enables the devices output data buffers during a read cycle. With
OE# at VIH, device data outputs are placed in High-Z state.
RESET: When low, RST# resets internal automation and inhibits write operations. This provides data
protection during power transitions. RST#-high enables normal operation. Exit from reset places the
device in asynchronous read array mode.
WAIT: Indicates data valid in synchronous read modes. Configuration Register bit 10 (CR.10, WT)
determines its polarity when set to 1. With CE# at VIL, WAITs active output is VOL or VOH. WAIT is
High-Z if CE# is VIH. WAIT is not gated by OE#.
WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the
WE# pulses rising edge.
WRITE PROTECT: Disables/enables the lock-down function.
When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot
be unlocked through software.
See Section 4.12, Block Locking Commandson page 27 for details on block locking.
ERASE AND PROGRAM POWER: A valid VPP voltage on this pin allows erase or programming.
Memory contents cannot be altered when VPP VPPLK. Block erase and program at invalid VPP
voltages should not be attempted.
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, VPPs VIH level can be as low as VPP1 min. VPP must remain above VPP1 min
to perform in-system flash modification. VPP may be 0 V during read operations.
VPP2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.
VPP can be connected to 12 V for a cumulative total not to exceed 80 hours maximum. Extended use
of this pin at 12 V may reduce block cycling capability.
DEVICE POWER SUPPLY: Writes are inhibited at VCC VLKO. Device operations at invalid VCC
voltages should not be attempted.
OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ. This input may be tied directly to
VCC.
GROUND: Pins for all internal device circuitry must be connected to system ground.
OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal may be tied
directly to VSS.
DONT USE: Do not use this pin. This pin should not be connected to any power supplies, signals or
other pins and must be floated.
NO CONNECT: No internal connection; can be driven or floated.
Preliminary
5

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