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PDF CD1865 Data sheet ( Hoja de datos )

Número de pieza CD1865
Descripción Intelligent Eight-channel Communications Controller
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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CD1865
Intelligent Eight-Channel Communications Controller
Datasheet
Product Features
s Eight full-duplex asynchronous channels s Software compatibility with the CD180 and
supporting data rates up to 115.2 kbps
Note: To support this data rate, the
specified system clock frequency is
mrequired.
os Register-based interrupt acknowledges
eliminate need for separate interrupt
.cacknowledge signals
s Automatic prioritizing scheme allows
device to respond to an interrupt
Uacknowledge with the highest internal
interrupt pending (host-programmable)
t4s Sophisticated interrupt schemes
— Vectored interrupts
e—Fair Share interrupts
— Good Datainterrupts for improved
ethroughput
h—Simultaneous interrupt requests for three
classes of interrupts: Rx, Tx, and
Smodem state changes
s Independent baud-rate generators for each
tachannel/direction
CD1864 devices
s Generation and detection of special
characters
s Automatic flow control
— In-band (Xon, Xoff generation, and
detection)
— Out-of-band (DTR/DSR or RTS/CTS)
s On-chip FIFO — 8 bytes each for Rx, Tx,
and Status
s Line break detection and generation
s Multiple-chip daisy-chain cascading
feature
s Odd, even, forced, or no parity
s modem/general-purpose I/O signals per
channel
s System clock up to 66 MHz (x2), 33MHz
(x1)
s CMOS technology in 100-pin MQFP
www.Da .DataSheet4U.comAs of May 18, 2001, this document replaces the Basis
wwwCommunications Corp. document CL-CD1865 — Intelligent 8-Channel Communications Controller. May 2001

1 page




CD1865 pdf
9.0
10.0
Intelligent Eight-Channel Communications Controller CD1865
8.9
8.10
8.11
Transmitting Data ................................................................................................87
Receiving Data ....................................................................................................88
Programming Examples ......................................................................................88
8.11.1 Programming the Service Match Registers ............................................88
8.11.2 CD1865 Initialization ..............................................................................88
8.11.3 Basic I/O Operations ..............................................................................90
8.11.4 Interrupt Response Operations ..............................................................90
8.11.5 Polled Mode Operation...........................................................................93
Detailed Register Descriptions...........................................................................94
9.1 Register Map Quick Reference ...........................................................................94
9.2 Global Registers..................................................................................................97
9.2.1 Miscellaneous Registers ........................................................................98
9.2.2 Configuration Registers..........................................................................98
9.2.3 Service Request/Interrupt Control Registers ........................................103
9.3 Indexed Indirect Registers.................................................................................108
9.3.1 Receive Data Count Register...............................................................108
9.3.2 Receive Data Register .........................................................................109
9.3.3 Receive Character Status Register ......................................................110
9.3.4 Transmit Data Register ........................................................................111
9.3.5 End-of-Service Request Register.........................................................111
9.4 Channel Registers.............................................................................................111
9.4.1 Enable Register...................................................................................112
9.4.2 Channel Command Register ................................................................112
9.4.3 Channel Option Register 1 ...................................................................116
9.4.4 Channel Option Register 2 ...................................................................116
9.4.5 Channel Option Register 3 ...................................................................117
9.4.6 Channel Control Status Register..........................................................118
9.4.7 Receiver Bit Register............................................................................119
9.4.8 Receive Time-Out Period Register.......................................................120
9.4.9 Receive Bit Rate Period Registers (High/Low).....................................120
9.4.10 Transmit Bit Rate Period Registers (High/Low)....................................121
9.4.11 Special Character Register 1 ...............................................................121
9.4.12 Special Character Register 2 ...............................................................122
9.4.13 Special Character Register 3 ...............................................................122
9.4.14 Special Character Register 4 ...............................................................123
9.4.15 Modem Change Register .....................................................................123
9.4.16 Modem Change Option Register 1.......................................................124
9.4.17 Modem Change Option Register 2.......................................................125
9.4.18 Modem Signal Value Register..............................................................125
9.4.19 Modem Signal Value Request-to-Send Register..................................126
9.4.20 Modem Signal Value Data-Terminal-Ready Register ..........................126
Electrical Specifications ....................................................................................127
10.1
10.2
10.3
10.4
10.5
Absolute Maximum Ratings...............................................................................127
Recommended Operating Conditions ...............................................................127
DC Electrical Characteristics.............................................................................127
Index of Timing Information...............................................................................128
AC Electrical Characteristics .............................................................................128
10.5.1 Clocked Bus Interface ..........................................................................128
Datasheet
5

5 Page





CD1865 arduino
Intelligent Eight-Channel Communications Controller CD1865
CPU
ADDRESS
DECODE
AND
CONTROL
LOGIC
INTERRUPT
CONTROLLER
ADDRESS
DATA
CS*
DS*
R/W
DTACK*
ACKIN*
TxD
RxD
DTR*
DSR*
RTS*
CTS*
CD*
CD1865
RREQ*
TREQ*
MREQ*
Channel 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
Typical CD1865 Host CPU Interface
INTERRUPT
CONTROLLER
CPU
ACKIN* ACKOUT* ACKIN* ACKOUT* ACKIN* ACKOUT*
CD1865
CD1865
CD1865
CD1865 in Daisy-Chain Scheme
Because the CD1865 RISC processor is processing every character sent or received, features such
as automatic flow control and special character recognition are easily implemented. This further
reduces the processing burden on the host system. Both In-Band (Xon, Xoff) and Out-of-Band
(RTS/CTS, DTR) Flow-Control modes are supported. For in-band flow control, the CD1865
automatically starts and stops its transmitter when the remote unit sends flow-control characters.
The CD1865 also makes it easy for the local host to flow-control the remote, by the send special
charactercommands. For out-of-band flow control, the transmitter optionally asserts RTS and
monitor CTS for permission to send; and assert/negate DTR when the Receive FIFO reaches a
user- definable threshold. Together, the in-band and out-of-band features not only allow the data
flow to be controlled in real time with minimum or no host intervention, it also prevents loss of
data.
As shown on the previous page, the CD1865 can interface virtually any CPU, with a minimum of
glue logic. Refer to the CD1865 Data Sheet for detailed information on how to interface various
microprocessors. Systems with multiple CD1865s are easily implemented, with no external glue,
by device a daisy-chain scheme. A fair sharefeature ensures equal access for all service requests,
both within one CD1865 and across multiple devices.
FIFO 24 bytes of FIFO are dedicated to each channel partitioned as 8 bytes for transmitter,
8 bytes for receiver, and 8 bytes for status. The receive FIFO has a user-programmable threshold to
optimize system response and latency. The receive FIFO threshold programming range is from 18
characters.
Vectored Interrupt Structure Three interrupt signals ([R, T, M]REQ*) are used. These signals
may also be read as an on-device register. Each REQ* signal represents one of three interrupt
groups: receive, transmit, and modem signal state changes. Upon servicing by the host, an interrupt
vector is generated by the CD1865 to define the interrupt group to be serviced and which CD1865
generated the interrupt. This allows the host software to enter directly into the proper interrupt
service routine, reducing the amount of interaction between the host and the controller, and
determining the nature of the interrupt.
Good Data Interrupt If data received is all good, the host is advised of the number of good
data bytes in the FIFO, allowing the host to read data without further status queries until all good
data has been transferred.
Fair-Share Interrupt Scheme To ensure equal service of all channels, a fair share scheme is
used for each interrupt group. No channel can interrupt for the same condition until all others have
a chance to be serviced for the same interrupt condition.
Datasheet
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