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PDF nl10276bc24_13 Data sheet ( Hoja de datos )

Número de pieza nl10276bc24_13
Descripción TFT COLOR LCD MODULE
Fabricantes NEC 
Logotipo NEC Logotipo



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Gleichmann & Co. Electronics GmbH
Product Marketing Displays & Systems
Industriestr. 16, D- 76297 Stutensee
Tel :07249-910-0, Fax: 07249-910-559
http://www.msc-ge.com
omTFT COLOR LCD MODULE
U.cN L 1 0 2 7 6 B C 2 4 - 1 3
et430.7cm (12.1 Type)
eXGA
hLVDS interface (1port)
ataSDATA SHEET
www.DDOD-PD-0331 (2nd edition)
eet4U.comThis DATA SHEET is updated document from
hDOD-PD-0309(1).
taSAll information is subject to change without notice.
aPlease confirm the sales representative before
.Dstarting to design your system.
wwDocument Number: DOD-PD-0331 (2nd edition)
wPublished date: December 2003 CP(N)
1
NEC LCD Technologies, Ltd.
2003 All rights reserved.

1 page




nl10276bc24_13 pdf
NL10276BC24-13
2. GENERAL SPECIFICATIONS
Display area
Diagonal size of display
Drive system
Display color
Pixel
Pixel arrangement
Dot pitch
Pixel pitch
Module size
Weight
Contrast ratio
Viewing angle
Designed viewing direction
Polarizer surface
Polarizer pencil-hardness
Color gamut
Response time
Luminance
Signal system
Power supply voltage
245.76 (H) × 184.32 (V) mm
30.7 cm (12.1 inches)
a-Si TFT active matrix
At input signals for data of RGB: 8bit and FRC: High
16,777,216 colors
At input signals for data of RGB: 6bit and FRC: Low or Open
262,144 colors
1,024 (H) × 768 (V) pixels
RGB (Red dot, Green dot, Blue dot) vertical stripe
0.08 (H) × 0.24 (V) mm
0.24 (H) × 0.24 (V) mm
280.0 (W) × 210.0 (H) × 13.0 (D) mm (typ.)
750g (typ.)
600:1 (typ.)
At the contrast ratio 10:1
Horizontal: Right side 70° (typ.), Left side 70° (typ.)
Vertical: Up side 45° (typ.), Down side 55° (typ.)
At DPS= Low or Open: normal scan
Viewing direction without image reversal: up side (12 o'clock)
Viewing direction with contrast peak: down side (6 o'clock)
Viewing angle with optimum grayscale (γ=2.2): normal axis
Clear
3H (min.) [by JIS K5400]
At LCD panel center
40 % (typ.) [against NTSC color space]
Ton + Toff (10% ←→ 90%)
33 ms (typ.)
At lamp current IBL=5.0mArms / lamp
400 cd/m2 (typ.)
LVDS 1port (Receiver: THC63LVDF84A, THine Electronics Inc. or
equivalent)
8bit/6bit digital signals for data of RGB colors, Dot clock (CLK),
Data enable (DE)
LCD panel signal processing board: 3.3V
Edge light type: 2 cold cathode fluorescent lamps
Backlight
Replaceable parts
Lamp holder set: Type No. 121LHS18
Power consumption
Recommended inverter (Option)
Inverter: Type No. 121PW181
At lamp current IBL=5.0mArms / lamp and checkered flag pattern
7.0 W (typ., Power dissipation of the inverter does not include.)
DATA SHEET DOD-PD-0331 (2nd edition)
5

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nl10276bc24_13 arduino
NL10276BC24-13
4.4 POWER SUPPLY VOLTAGE SEQUENCE
4.4.1 LCD panel signal processing board
VCC
Note1
0V
ON
3.0V
10µsTr < 50ms
Display signals*
Function signals
Note2
0V
0ms < t < 35ms
VALID period
OFF
0.3V
Toff 50ms
0ms < t < 35ms
* These signals should be measured at the terminal of 100resistance.
Note1: In terms of voltage variation (voltage drop) while VCC rising edge is below 3.0V, a
protection circuit may work, and then this product may not work.
Note2: Display signals (D0+/-, D1+/-, D2+/-, D3+/- and CK+/-) and function signals (DPS and
FRC) must be Low or High-impedance, exclude the VALID period (See above sequence
diagram), in order to avoid that internal circuits is damaged.
If some of display and function signals of this product are cut while this product is
working, even if the signal input to it once again, it might not work normally. If customer
stops the display and function signals, they should be cut VCC.
4.4.2 Backlight inverter (Option)
Display and
function signals
Note1
Note2
VALID period
VDDB
Note1: These are the display and function signals for LCD panel signal processing board.
Note2: The backlight inverter voltage (VDDB) should be inputted within the valid period of
display and function signals, in order to avoid unstable data display.
DATA SHEET DOD-PD-0331 (2nd edition)
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