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PDF W134M Data sheet ( Hoja de datos )

Número de pieza W134M
Descripción (W134M/S) Direct Rambus Clock Generator
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! W134M Hoja de datos, Descripción, Manual

W134M/W134S
Direct Rambus™ Clock Generator
Features
Description
• Differential clock source for Direct Rambus™ memory The Cypress W134M/W134S provides the differential clock
subsystem for up to 800-MHz data transfer rate
signals for a Direct Rambus memory subsystem. It includes
• Provide synchronization flexibility: the Rambus®
Channel can optionally be synchronous to an external
system or processor clock
• Power-managed output allows Rambus Channel clock
to be turned off to minimize power consumption for
mmobile applications
• Works with Cypress CY2210, W133, W158, W159, W161,
oand W167 to support Intel® architecture platforms
.c• Low-power CMOS design packaged in a 24-pin QSOP
(150-mil SSOP) package
signals to synchronize the Direct Rambus Channel clock to an
external system clock but can also be used in systems that do
not require synchronization of the Rambus clock.
t4UBlock Diagram
eREFCLK
eMULT0:1
PLL
taShPCLKM
.DaSYNCLKN
Phase
Alignment
Output
Logic
CLK
CLKB
Pin Configuration
VDDIR
REFCLK
VDD
GND
GND
PCLKM
SYNCLKN
GND
VDD
VDDIPD
STOPB
PWRDNB
1
2
3
4
5
6
7
8
9
10
11
12
24 S0
23 S1
22 VDD
21 GND
20 CLK
19 NC
18 CLKB
17 GND
16 VDD
15 MULT0
14 MULT1
13 GND
www .comS0:1
t4USTOPB
Test
Logic
ww.DataSheeCypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
wDocument #: 38-07426 Rev. *C
Revised June 1, 2005

1 page




W134M pdf
W134M/W134S
Table 4. Bypass and Test Mode Selection
Mode
Bypclk
S0 S1 (int.) Clk
ClkB
Normal
0 0 Gnd PAclk PAclkB
Output Test (OE) 0 1 – Hi-Z Hi-Z
Bypass
1 0 PLLclk PLLclk PLLclkB
Test 1 1 Refclk Refclk RefclkB
Table 5 shows the logic for selecting the Power-down mode,
using the PwrDnB input signal. PwrDnB is active LOW
(enabled when 0). When PwrDnB is disabled, the DRCG is in
its normal mode. When PwrDnB is enabled, the DRCG is put
into a powered-off state, and the Clk and ClkB outputs are
three-stated.
Table 5. Power-down Mode Selection
Mode
Normal
Power-down
PwrDnB
1
0
Clk
PAclk
GND
ClkB
PAclkB
GND
Table of Frequencies and Gear Ratios
Table 6 shows several supported Pclk and Busclk
frequencies, the corresponding A and B dividers required in
the DRCG PLL, and the corresponding M and N dividers in the
gear ratio logic. The column Ratio gives the Gear Ratio as
defined Pclk/Synclk (same as M and N). The column F@PD
gives the divided down frequency (in MHz) at the Phase
Detector, where F@PD = Pclk/M = Synclk/N.
State Transitions
The clock source has three fundamental operating states.
Figure 4 shows the state diagram with each transition labelled
A through H. Note that the clock source output may NOT be
glitch-free during state transitions.
Upon powering up the device, the device can enter any state,
depending on the settings of the control signals, PwrDnB and
StopB.
In Power-down mode, the clock source is powered down with
the control signal, PwrDnB, equal to 0. The control signals S0
and S1 must be stable before power is applied to the device,
and can only be changed in Power-down mode (PwrDnB = 0).
The reference inputs, VDDR and VDDPD, may remain on or may
be grounded during the Power-down mode.
Table 6. Examples of Frequencies, Dividers, and Gear Ratios
Pclk
67
100
100
133
133
Refclk
33
50
50
67
67
Busclk
267
300
400
267
400
Synclk
67
75
100
67
100
A BMN
8122
6186
8144
4142
6186
Ratio
1.0
1.33
1.0
2.0
1.33
F@PD
33
12.5
25
33
16.7
The control signals Mult0 and Mult1 can be used in two ways.
If they are changed during Power-down mode, then the
Power-down transition timings determine the settling time of
the DRCG. However, the Mult0 and Mult1 control signals can
also be changed during Normal mode. When the Mult control
signals are “hot-swapped” in this manner, the Mult transition
timings determine the settling time of the DRCG.
In Normal mode, the clock source is on, and the output is
enabled.
Table 7 lists the control signals for each state.
Table 7. Control Signals for Clock Source States
State
Power-down
Clock Stop
Normal
PwrDnB
0
1
1
StopB
X
0
1
Clock
Source
OFF
ON
ON
Output
Buffer
Ground
Disabled
Enabled
Figure 5 shows the timing diagrams for the various transitions
between states, and Table 8 specifies the latencies of each
state transition. Note that these transition latencies assume
the following.
Refclk input has settled and meets specification shown in the
Operating Conditions table.
The Mult0, Mult1, S0 and S1 control signals are stable.
VDD Turn-On
M
VDD Turn-On
GJ
L
Test
K
N
B
A
VDD Turn-On
Power-Down
Normal
E
D
C
F
Clk Stop
Figure 4. Clock Source State Diagram
Document #: 38-07426 Rev. *C
VDD Turn-On
H
Page 5 of 12

5 Page





W134M arduino
Package Diagram
24-Lead Quarter Size Outline Q13
W134M/W134S
51-85055-*B
Direct Rambus is a trademark and Rambus is a registered trademark of Rambus Inc. Intel is a registered trademark of Intel
Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07426 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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