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PDF TC58NVG1S8BFT00 Data sheet ( Hoja de datos )
| Número de pieza | TC58NVG1S8BFT00 | |
| Descripción | (TC58NVG1S3BFT00) 2 GBit CMOS NAND EPROM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TC58NVG1S8BFT00 (archivo pdf) en la parte inferior de esta página. Total 37 Páginas | ||
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TC58NVG1S3BFT00/TC58NVG1S8BFT00
omTENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
U.c2 GBIT (256M × 8 BIT/128M × 16 BIT) CMOS NAND E2PROM
et4DESCRIPTION
heThe TC58NVG1SxB is a single 3.3 V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable
SRead-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes/(1024 + 32) words × 64 pages × 2048 blocks.
taThe device has a 2112-byte/1056-word static register which allow program and read data to be transferred between
athe register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single
block unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages).
.DThe TC58NVG1SxB is a serial-type memory device which utilizes the I/O pins for both address and data
winput/output as well as for command inputs. The Erase and Program operations are automatically executed making
wthe device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
w cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
m• Organization
oMemory cell array
.cRegister
Page size
Block size
TC58NVG1S3B
2112 × 128K × 8
2112 × 8
2112 bytes
(128K + 4K) bytes
TC58NVG1S8B
1056 × 128K × 16
1056 × 16
1056 words
(64K + 2K) words
U• Modes
t4Read, Reset, Auto Page Program, Auto Block Erase Status Read
• Mode control
eSerial input/output
Command control
e• Number of valid blocks
hMax 2048 blocks
Min 2008 blocks
S• Power supply
taVCC = 2.7 V to 3.6 V
a• Program/Erase Cycles
100000 Cycles (With ECC)
.D• Access time
Cell array to register 25 µs max
Serial Read Cycle
50 ns min
w• Program/Erase time
wAuto Page Program
wAuto Block Erase
200 µs/page typ.
1.5 ms/block typ.
• Operating current
Read (50 ns cycle)
Program (avg.)
Erase (avg.)
Standby
10 mA typ.
10 mA typ.
10 mA typ.
50 µA max
• Package
TC58NVG1S3BFT00 TSOP I 48-P-1220-0.50
TC58NVG1S8BFT00 TSOP I 48-P-1220-0.50
(Weight: 0.53 g typ.)
1
www.DataSh20e0e3-t140U-30.cAom
1 page  
TC58NVG1S3BFT00/TC58NVG1S8BFT00
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70 , VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
tCLS
tCLH
tCS
tCH
tWP
tALS
tALH
tDS
tDH
tWC
tWH
tWW
tRR
tRW
tRP
tRC
tREA
tCEA
tCLEA
tALEA
tOH
tRHZ
tCHZ
tREH
tIR
tRHW
tWHC
tWHR
tR
tWB
tRST
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
WP High to WE Low
Ready to RE Falling Edge
Ready to WE Falling Edge
Read Pulse Width
Read Cycle Time
RE Access Time
CE Access Time
CLE Access Time
ALE Access Time
Data Output Hold Time
RE High to Output High Impedance
CE High to Output High Impedance
RE High Hold Time
Output-High-impedance-to- RE Falling Edge
RE High to WE Low
WE High to CE Low
WE High to RE Low
Memory Cell Array to Starting Address
WE High to Busy
Device Reset Time (Ready/Read/Program/Erase)
MIN
MAX
UNIT
0
10
0
10
25
0
10
20
10
50
15
100
20
20
35
50
35
45
45
45
10
30
20
15
0
30
30
30
25
200
6/6/10/500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
NOTES
5 2003-10-30A
5 Page 
TC58NVG1S3BFT00/TC58NVG1S8BFT00
Column Address Change in Read Cycle Timing Diagram (1/2)
CLE
CE
tCLS tCLH
tCS tCH
WE
tWC
tCLS tCLH
tCS tCH
tCLEA
tCEA
tALH tALS
tALH
tALS
ALE
RE
tDS tDH
tR
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
tWB
tDS tDH
tRC
tRR tREA
I/O
RY / BY
00h
CA0
to 7
CA8
to 11
PA0
to 7
PA8
to 15
PA16
30h
Column address
A
Page address
P
DOUT DOUT DOUT
A A+1 A+N
Page address
P
Column address
A
1
Continues from 1 of next page
11 2003-10-30A
11 Page | ||
| Páginas | Total 37 Páginas | |
| PDF Descargar | [ Datasheet TC58NVG1S8BFT00.PDF ] | |
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