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PDF DP8391 Data sheet ( Hoja de datos )

Número de pieza DP8391
Descripción Serial Network Interface
Fabricantes National Semiconductor 
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No Preview Available ! DP8391 Hoja de datos, Descripción, Manual

.com July 1986
DPt8a3S9h1 eNeSt342U491 Serial Network InterfaceGeneral Description
The DP8391 Serial Network Interface (SNI) provides the
aManchester data encoding and decoding functions for
.DIEEE 802 3 Ethernet Cheapernet type local area networks
The SNI interfaces the DP8390 Network Interface Controller
w (NIC) to the Ethernet transceiver cable When transmitting
the SNI converts non-return-to-zero (NRZ) data from the
w controller and clock pulses into Manchester encoding and
w sends the converted data differentially to the transceiver
The opposite process occurs on the receive path where a
mdigital phase-locked loop decodes 10 Mbit s signals with as
much as g20 ns of jitter
oThe DP8391 SNI is a functionally complete Manchester en-
coder decoder including ECL like balanced driver and re-
ceivers on board crystal oscillator collision signal transla-
.ctor and a diagnostic loopback circuit
The SNI is part of a three chip set that implements the com-
plete IEEE compatible network node electronics as shown
below The other two chips are the DP8392 Coax Transceiv-
Uer Interface (CTI) and the DP8390 Network Interface Con-
troller (NIC)
t4Incorporated into the CTI are the transceiver collision and
jabber functions The Media Access Protocol and the buffer
management tasks are performed by the NIC There is an
eisolation requirement on signal and power lines between the
CTI and the SNI This is usually accomplished by using a set
eof miniature pulse transformers that come in a 16-pin plastic
DIP for signal lines Power isolation however is done by
taShusing a DC to DC converter
Features
Y Compatible with Ethernet II IEEE 802 3 10base5 and
10base2 (Cheapernet)
Y 10 Mb s Manchester encoding decoding with receive
clock recovery
Y Patented digital phase locked loop (DPLL) decoder re-
quires no precision external components
Y Decodes Manchester data with up to g20 ns of jitter
Y Loopback capability for diagnostics
Y Externally selectable half or full step modes of opera-
tion at transmit output
Y Squelch circuits at the receive and collision inputs re-
ject noise
Y High voltage protection at transceiver interface (16V)
Y TTL MOS compatible controller interface
Y Connects directly to the transceiver (AUI) cable
Table of Contents
1 0 System Diagram
2 0 Block Diagram
3 0 Functional Description
3 1 Oscillator
3 2 Encoder
3 3 Decoder
3 4 Collision Translator
3 5 Loopback
4 0 Connection Digram
5 0 Pin Description
6 0 Absolute Maximum Ratings
7 0 Electrical Characteristics
8 0 Switching Characteristics
9 0 Timing and Load Diagrams
10 0 Physical Dimensions
a1 0 System Diagram
.DIEEE 802 3 Compatible Ethernet Cheapernet Local Area Network Chip Set
www www.DataSheet4U.comC1995NationalSemiconductorCorporation TL F 6758
TL F 6758 – 1
RRD-B30M115 Printed in U S A

1 page




DP8391 pdf
6 0 Absolute Maximum Ratings
Supply Voltage (VCC)
Input Voltage (TTL)
6V
0 to 5 5V
Input Voltage (differential)
b5 5 to a16V
Output Voltage (differential)
0 to 16V
Output Current (differential)
b40 mA
Storage Temperature
b65 to 150 C
Lead Temperature (soldering 10 sec)
300 C
Package Power Rating at 25 C
(PC Board Mounted)
Derate Linearly at the rate of 23 8 mW C
2 95W
For actual power dissipation of the device please refer to Section 7 0
ESD rating is to be determined
Recommended Operating
Conditions
Supply Voltage (VCC)
Ambient Temperature
5V g 5%
0 to 70 C
Note Absolute maximum ratings are those values beyond
which the safety of the device cannot be guaranteed They
are not meant to imply that the device should be operated at
these limits
7 0 Electrical Characteristics VCC e 5V g5% TA e 0 to 70 C (Notes 1
Symbol
Parameter
Test Conditions
VIH Input High Voltage (TTL and X1)
VIL Input Low Voltage (TTL and X1)
IIH Input High Current (TTL)
Input High Current (RXg CDg)
IIL Input Low Current (TTL)
Input Low Current (RXg CDg)
VCL Input Clamp Voltage (TTL)
VOH Ouptut High Voltage (TTL MOS)
VOL Output Low Voltage (TTL MOS)
IOS Output Short Circuit Current (TTL MOS)
VOD Differential Output Voltage (TXg)
VIN e VCC
VIN e VCC
VIN e 0 5V
VIN e 0 5V
IIN e b12 mA
IOH e b100 mA
IOL e 8 mA
78X termination and
270X from each to GND
VOB
VDS
VCM
ICC
Diff Output Voltage Imbalance (TXg)
Diff Squelch Threshold (RXg CDg)
Diff Input Common Mode Voltage (RXg CDg)
Power Supply Current
same as above
10Mbit s
2)
Min
20
35
b40
g500
b175
5 25
Max
08
50
500
b300
b700
b1 2
05
b200
g1200
g40
b300
5 25
270
Units
V
V
mA
mA
mA
mA
V
V
V
mA
mV
mV
mV
V
mA
8 0 Switching Characteristics VCC e 5V g5% TA e 0 to 70 C (Note 2)
Symbol
Parameter
Figure Min Typ Max Units
OSCILLATOR SPECIFICATION
tXTH
X1 to Transmit Clock High
tXTL X1 to Transmit Clock Low
TRANSMIT SPECIFICATION
12 8
12 8
20 ns
20 ns
tTCd Transmit Clock Duty Cycle at 50% (10 MHz)
12 42 50 58 %
tTCr Transmit Clock Rise Time (20% to 80%)
12
8 ns
tTCf Transmit Clock Fall Time (80% to 20%)
12
8 ns
tTDs
Transmit Data Setup Time to Transmit Clock Rising Edge
4 12
20
ns
tTDh
Transmit Data Hold Time from Transmit Clock Rising Edge
4 12
0
ns
tTEs
Transmit Enable Setup Time to Trans Clock Rising Edge
4 12
20
ns
tTEh
Transmit Enable Hold Time from Trans Clock Rising Edge
5 12
0
ns
tTOd
Transmit Output Delay from Transmit Clock Rising Edge
4 12
40 ns
tTOr Transmit Output Rise Time (20% to 80%)
12
7 ns
tTOf Transmit Output Fall Time (80% to 20%)
12
7 ns
tTOj Transmit Output Jitter
12 g0 25 ns
tTOh
Transmit Output High Before Idle in Half Step Mode
5 12
200
ns
tTOi Transmit Output Idle Time in Half Step Mode
5 12
800 ns
Note 1 All currents into device pins are positive all currents out of device pins are negative All voltages are referenced to ground unless otherwise specified
Note 2 All typicals are given for VCC e 5V and TA e 25 C
5

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