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PDF NT256D64S88A2GM Data sheet ( Hoja de datos )

Número de pieza NT256D64S88A2GM
Descripción 256MB DDR SO-DIMM
Fabricantes Nanya Technology 
Logotipo Nanya Technology Logotipo



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NT256D64S88A2GM
256MB : 32M x 64
omPC2100 / PC1600 Unbuffered DDR SO-DIMM
U.c200pin One Bank Unbuffered DDR SO-DIMM Based on DDR266/200 32Mx8 SDRAM
eet4Features
h• JEDEC Standard 200-Pin Small Outline Dual In-Line Memory
SModule (SO-DIMM)
ta• 32Mx64 Double Unbuffered DDR SO-DIMM based on 32Mx8
aDDR SDRAM.
.D• Performance :
w PC1600
PC2100
w Speed Sort
- 8B - 75B - 7K Unit
w DIMM CAS Latency
2 2.5 2
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock
transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
f CK Clock Frequency
100 133 133
t CK Clock Cycle
10 7.5 7.5
f DQ DQ Burst Frequency 200 266 266
m• Intended for 100 MHz and 133 MHz applications
o• Inputs and outputs are SSTL-2 compatible
• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2
.c•Single Pulsed RAS interface
• SDRAMs have 4 internal banks for concurrent operation
• Module has one physical bank
U• Differential clock inputs
MHz
ns
MHz
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/10/2 Addressing (row/column/bank)
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
t4Description
eNT256D64S88A2GM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
eorganized as a one-bank high-speed memory array. The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR
hSDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use
in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all
Sdevices on the DIMM.
taPrior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by
aaddress inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
.Ddesign files minimizes electrical variation between suppliers.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
wdata are programmed and locked during module assembly. The last 128 bytes are available to the customer.
wAll NANYA 200pin DDR SO-DIMMs provide a high-performance, flexible 8-byte interface in a 2.66” long space-saving footprint.
wOrdering Information
mPart Number
.coNT256D64S88A2GM-7K
et4UNT256D64S88A2GM-75B
SheNT256D64S88A2GM-8B
Speed
143MHz (7ns @ CL = 2.5 )
133MHz (7.5ns @ CL= 2 )
133MHz (7.5ns @ CL= 2.5 )
100MHz (10ns @ CL = 2 )
125MHz (8ns @ CL = 2.5 )
100MHz (10ns @ CL = 2 )
PC2100
PC2100
PC1600
Organization
32Mx64
Leads
Gold
Power
2.5V
www.DataPreliminary 01 / 2002
1
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

1 page




NT256D64S88A2GM pdf
NT256D64S88A2GM
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DDR SO-DIMM
Serial Presence Detect -- Part 1 of 2
Byte Description
0
1
2
3
4
5
6.
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
Number of Serial PD Bytes Written during
Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Bank
Data Width of Assembly
Data Width of Assembly (cont’)
Voltage Interface Level of this Assembly
DDR SDRAM Device Cycle Time at CL=2.5
DDR SDRAM Device Access Time from
Clock at CL=2.5
DIMM Configuration Type
Refresh Rate/Type
Primary DDR SDRAM Width
Error Checking DDR SDRAM Device Width
DDR SDRAM Device Attr: Min CLk Delay,
Random Col Access
DDR SDRAM Device Attributes:
Burst Length Supported
DDR SDRAM Device Attributes: Number of
Device Banks
DDR SDRAM Device Attributes: CAS
Latencies Supported
DDR SDRAM Device Attributes: CS Latency
DDR SDRAM Device Attributes: WE Latency
DDR SDRAM Device Attributes:
DDR SDRAM Device Attributes: General
Minimum Clock Cycle at CL=2
Maximum Data Access Time from Clock at
CL=2
Minimum Clock Cycle Time at CL=1
Maximum Data Access Time from Clock at
CL=1
Minimum Row Precharge Time(tRP)
Minimum Row Active to Row Active delay
(tRRD)
Minimum RAS to CAS delay (tRCD)
Minimum RAS Pulse Width (tRAS)
Module Bank Density
Address and Command Setup Time Before
Clock
Address and Command Hold Time After
Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
Reserved
SPD Revision
Checksum Data
SPD Entry Value
DDR266A DDR266B DDR200
-7K -75B -8B
128
256
SDRAM DDR
13
10
1
X64
X64
SSTL 2.5V
7ns 7.5ns 8ns
0.75ns 0.75ns
0.8ns
Non-Parity
SR/1x(7.8us)
X8
N/A
1 Clock
2,4,8
4
2/2.5
2/2.5
2/2.5
0
1
Differential Clock
+/-0.2V Voltage Tolerance
7.5ns
10ns
10ns
0.75ns 0.75ns
0.8ns
N/A
N/A
20ns
20ns
20ns
15ns
15ns
15ns
20ns
45ns
20ns
45ns
256MB
20ns
50ns
0.9ns
0.9ns
1.1ns
0.9ns
0.5ns
0.5ns
Initial
0.9ns
0.5ns
0.5ns
Undefined
Initial
1.1ns
0.6ns
0.6ns
Initial
Serial PD Data Entry (Hexadecimal)
DDR266A DDR266B DDR200
-7K -75 -8B
Note
80
08
07
0D
0A
01
40
00
04
70 75 80
75 75 80
00
82
08
00
01
0E
04
0C 0C 0C
01
02
20
00
75 A0 A0
75 75 80
00
00
50 50 50
3C 3C 3C
50 50 50
2D 2D 32
40
90 90 B0
90 90 B0
50 50 60
50 50 60
00
00 00 00
8F BF 45
Preliminary 01 / 2002
5
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

5 Page





NT256D64S88A2GM arduino
NT256D64S88A2GM
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DDR SO-DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
Symbol
Parameter
-7K
Min. Max.
-75B
Min. Max.
-8B
Min. Max.
tAC DQ output access time from CK/ CK
-0.75 +0.75 -0.75 +0.75 -0.8
+0.8
tDQSCK DQS output access time from CK/ CK
-0.75 +0.75 -0.75 +0.75 -0.8
+0.8
tCH CK high-level width
0.45 0.55 0.45 0.55 0.45 0.55
tCL CK low-level width
0.45 0.55 0.45 0.55 0.45 0.55
tCK
Clock cycle time
tCK
CL=2.5
CL=2
7 12 7.5 12 8
7.5 12 10 12 10
12
12
tDH DQ and DM input hold time
0.5 0.5 0.6
tDS DQ and DM input setup time
tDIPW
tHZ
tLZ
tDQSQ
tDQSQA
tHP
tQH
tDQSS
tDQSL,H
tDSS
tDSH
tMRD
DQ and DM input pulse width (each input)
Data-out high-impedance time from
CK/ CK
Data-out low-impedance time from
CK/ CK
DQS-DQ skew (DQS & associated DQ
signals)
DQS-DQ skew (DQS & all DQ signals)
Minimum half clk period for any given
cycle; defined by clk high(tCH )
or clk low (tCL ) time
Data output hold time from DQS
Write command to 1st DQS latching
transition
DQS input low (high) pulse width
(write cycle)
DQS falling edge to CK setup time
(write cycle)
DQS falling edge hold time from CK
(write cycle)
Mode register set command cycle time
tWPRES Write preamble setup time
0.5
1.75
-0.75
+0.75
0.5
1.75
-0.75
+0.75
0.6
2
-0.8
-0.75 +0.75 -0.75 +0.75 -0.8
tCH
or
tCL
tHP -
0.75ns
0.75
0.5
0.5
1.25
tCH
or
tCL
tHP -
0.75ns
0.75
0.5
0.5
1.25
tCH
or
tCL
tHP -
1.0ns
0.75
0.35 0.35 0.35
0.2 0.2 0.2
0.2 0.2 0.2
14 15 16
000
+0.8
+0.8
0.6
0.6
1.25
tWPST
tWPRE
tIH
Write postamble
Write preamble
Address and control input hold time
(fast slew rate)
Address and control input setup time
tIS
(fast slew rate)
Address and control input hold time
tIH
(slow slew rate)
0.40 0.60 0.40 0.60 0.40 0.60
0.25 0.25 0.25
0.9 1.1 1.1
0.9 1.1 1.1
1.0 1.1 1.1
Unit Notes
ns 1,2,3,4
ns 1,2,3,4
tCK 1,2,3,4
tCK 1,2,3,4
ns 1,2,3,4
ns 1,2,3,4
1,2,3,4
ns
,15,16
1,2,3,4
ns
,15,16
ns 1,2,3,4
1, 2, 3,
ns
4, 5
1, 2, 3,
ns
4, 5
ns 1,2,3,4
ns 1,2,3,4
tCK 1,2,3,4
tCK 1,2,3,4
tCK 1,2,3,4
tCK 1,2,3,4
tCK 1,2,3,4
tCK 1,2,3,4
ns 1,2,3,4
1, 2, 3,
ns
4, 7
1, 2, 3,
tCK
4, 6
tCK 1,2,3,4
2, 3, 4,
ns 9, 11,
12
2, 3, 4,
ns 9, 11,
12
2, 3, 4,
ns 10, 11,
12, 14
Preliminary 01 / 2002
11
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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