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PDF BU-6186x Data sheet ( Hoja de datos )

Número de pieza BU-6186x
Descripción Enhanced Miniature Advanced Communications Engine
Fabricantes Data Device 
Logotipo Data Device Logotipo



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BU-6174X/6184X/6186X
ENHANCED MINIATURE ADVANCED
COMMUNICATIONS ENGINE
[ENHANCED MINI-ACE/µ-ACE (MICRO-ACE)]
µ-ACE
DESCRIPTION
The Enhanced Miniature Advanced Communications Engine (Enhanced
Mini-ACE) and µ-ACE (Micro-ACE) family of MIL-STD-1553 terminals pro-
vide complete interfaces between a host processor and a 1553 bus, and
integrate dual transceiver, protocol logic, and 4K or 64K words of RAM.
At 0.815" square, the µ-ACE (BGA package) option provides the
smallest footprint in the industry.
The terminals are powered by a choice of 5V or 3.3V logic.
Multiprotocol support of MIL-STD-1553A/B and STANAG 3838, includ-
ing versions incorporating McAir compatible transmitters, is provided.
There is a choice of 10, 12, 16, or 20 MHz clocks. The BC/RT/MT ver-
sions with 64K words of RAM include built-in RAM parity checking.
BC features include a built-in message sequence control engine, with
a set of 20 instructions. This feature provides an autonomous means
of implementing multi-frame message scheduling, message retry
schemes, data double buffering, asynchronous message insertion,
and reporting to the host CPU. The Enhanced Mini-ACE/µ-ACE incor-
porates a fully autonomous built-in self-test, providing comprehensive
testing of the internal protocol logic and/or RAM.
The RT offers the same choices of subaddress buffering as the ACE
and Mini-ACE (Plus), along with a global circular buffering option,
50% rollover interrupt for circular buffers, an interrupt status queue,
and an "Auto-boot" option to support MIL-STD-1760.
The terminals provide the same flexibility in host interface configura-
tions as the ACE/Mini-ACE, along with a reduction in the host proces-
sor's worst case holdoff time. Most software features are compatible
with the previous generations of the Mini-ACE (Plus) and ACE series.
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Make sure the next
Card you purchase
has...
®
FEATURES
Fully Integrated 1553A/B Notice 2,
McAir, STANAG 3838 Interface Terminal
Compatible with Mini-ACE (Plus)
and ACE Generations
Choice of :
- RT or BC/RT/MT In Same Footprint
- RT or BC/RT/MT with 4K RAM
- BC/RT/MT with 64K RAM, and RAM
parity
Choice of 5V or 3.3V Logic
• Package Options:
- 1" Square Ceramic Flat Pack or
Gull Wing
- 0.815" Square BGA (µ-ACE)
5V Transceiver with 1760 and McAir
Compatible Options
Comprehensive Built-In Self-Test
Flexible Processor/Memory Interface,
with Reduced Host Wait Time
Choice of 10, 12, 16, or 20 MHz Clock
Highly Autonomous BC with
Built-In Message Sequence Control:
- Frame Scheduling
- Branching
- Asynchronous Message Insertion
- General Purpose Queue
- User-defined Interrupts
Advanced RT Functions
- Global Circular Buffering
- Interrupt Status Queue
- 50% Circular Buffer Rollover
Interrupts
Selective Message Monitor
- Selection by Address, T/R Bit,
Subaddress
- Command and Data Stacks
- 50% and 100% Stack Rollover
Interrupts
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7771
© 2000 Data Device Corporation

1 page




BU-6186x pdf
(2) Impedance parameters are specified directly between pins TX/RX_A(B)
and TX/RX_A(B) of the Enhanced Mini-ACE/µ-ACE hybrid.
(3) It is assumed that all power and ground inputs to the hybrid are con-
nected.
(4) The specifications are applicable for both unpowered and powered
conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
(7) Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to hybrid
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
(8) Typical value for minimum intermessage gap time. Under software
control, this may be lengthened (to 65,535 ms - message time) in
increments of 1 µs. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic "1", then host accesses
during BC Start-of-Message (SOM) and End-of-Message (EOM)
transfer sequences could have the effect of lengthening the inter-
message gap time. For each host access during an SOM or EOM
sequence, the intermessage gap time will be lengthened by 6 clock
cycles. Since there are 7 internal transfers during SOM and 5 dur-
ing EOM, this could theoretically lengthen the intermessage gap by
up to 72 clock cycles; i.e., up to 7.2 ms with a 10 MHz clock, 6.0 µs
with a 12 MHz clock, 4.5 µs with a 16 MHz clock, or 3.6 µs with a
20 MHz clock.
(9) For Enhanced BC mode, the typical value for intermessage gap
time is approximately 10 clock cycles longer than for the non-
enhanced BC mode. That is, an addition of 1.0 µs at 10 MHz, 833
ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.
(10) Software programmable (4 options). Includes RT-to-RT Timeout
(measured mid-parity of transmit Command Word to mid-sync of
transmitting RT Status Word).
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12) External 10 µF tantalum and 0.1 µF capacitors should be located as
close as possible to input signals “+5V Vcc CH A” and “+5V Vcc CH
B”, and a 0.1 µF to input signal “+5V/+3.3V Logic”. For the BU-
61864 and BU-61865, and BU-61860 versions, there should also be
a 0.1 µF capacitor for the input signal “+5V RAM”.
(13) MIL-STD-1760 requires a 20 Vp-p minimum output on the stub con-
nection.
(14) Power dissipation specifications assume a transformer coupled
configuration with external dissipation (while transmitting) of:
0.14 watts for the active isolation transformer,
0.08 watts for the active bus coupling transformer,
0.45 watts for each of the two bus isolation resistors and
0.15 watts for each of the two bus termination resistors.
INTRODUCTION
The BU-61740/61743/61745 RT, and BU-61840/61843/61845/
61860/61864/61865 BC/RT/MT Enhanced Mini-ACE/µ-ACE
family of MIL-STD-1553 terminals comprise a complete integrat-
ed interface between a host processor and a MIL-STD-1553 bus.
The Enhanced Mini-ACE is available as a 1.0 square inch flat
pack or gull wing package. The µ-ACE is available as a 0.815
square inch BGA package. These terminals are nearly 100%
software compatible with the previous generation Mini-ACE and
Mini-ACE Plus terminals, and are software compatible with the
original ACE series.
The Enhanced Mini-ACE provides complete multiprotocol support of
MIL-STD-1553A/B/McAir and STANAG 3838. All versions integrate
a dual transceiver, along with protocol, host interface, memory man-
agement logic, and either 4K or 64K words of RAM. In addition, the
BU-61864 and BU-61865 BC/RT/MT terminals include 64K words
of internal RAM, with built-in parity checking.
The Enhanced Mini-ACE includes a 5V voltage source transceiv-
er for improved line driving capability, with options for MIL-STD-
1760 and McAir compatibility, and the µ-ACE is MIL-STD-1760
compatible. As a means of reducing power consumption, there
are versions for which the logic is powered by 3.3V, rather than
5V. To provide further flexibility, the Enhanced Mini-ACE/µ-ACE
may operate with a choice of 10, 12, 16, or 20 MHz clock inputs.
One of the new salient features of the Enhanced Mini-ACE/µ-ACE
is its Enhanced bus controller architecture. The Enhanced BC's
highly autonomous message sequence control engine provides
a means for offloading the host processor for implementing multi-
frame message scheduling, message retry schemes, data dou-
ble buffering, and asynchronous message insertion. For the pur-
pose of performing messaging to the host processor, the
Enhanced BC mode includes a General Purpose Queue, along
with user-defined interrupts.
A second major new feature of the Enhanced Mini-ACE/µ-ACE is
the incorporation of a fully autonomous built-in self-test. This test
provides comprehensive testing of the internal protocol logic. A
separate test verifies the operation of the internal RAM. Since
the self-tests are fully autonomous, they eliminate the need for
the host to write and read stimulus and response vectors.
The Enhanced Mini-ACE/µ-ACE RT offers the same choices of
single, double, and circular buffering for individual subaddresses
as ACE and Mini-ACE (Plus). New enhancements to the RT
architecture include a global circular buffering option for multiple
(or all) receive subaddresses, a 50% rollover interrupt for circu-
lar buffers, an interrupt status queue for logging up to 32 inter-
rupt events, and an option to automatically initialize to RT mode
with the Busy bit set. The interrupt status queue and 50% rollover
interrupt features are also included as improvements to the
Enhanced Mini-ACE/µ-ACE's Monitor architecture.
Data Device Corporation
BU-6174X/6184X/6186X
www.ddc-web.com
5
M-12/04-0

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BU-6186x arduino
TABLE 16. BC FRAME TIME REMAINING REGISTER
(READ/WRITE 0BH)
BIT DESCRIPTION
15(MSB) BC FRAME TIME REMAINING 15
••
••
••
0(LSB) BC FRAME TIME REMAINING 0
Note: resolution = 100 µs per LSB
TABLE 17. BC MESSAGE TIME REMAINING
REGISTER
(READ/WRITE 0CH)
BIT DESCRIPTION
15(MSB) BC MESSAGE TIME REMAINING 15
••
••
••
0(LSB) BC MESSAGE TIME REMAINING 0
Note: resolution = 1 µs per LSB
TABLE 20. RT BIT WORD REGISTER
(READ 0FH)
BIT DESCRIPTION
15(MSB) TRANSMITTER TIMEOUT
14 LOOP TEST FAILURE B
13 LOOP TEST FAILURE A
12 HANDSHAKE FAILURE
11 TRANSMITTER SHUTDOWN B
10 TRANSMITTER SHUTDOWN A
9 TERMINAL FLAG INHIBITED
8 BIT TEST FAIL
7 HIGH WORD COUNT
6 LOW WORD COUNT
5 INCORRECT SYNC RECEIVED
4 PARITY / MANCHESTER ERROR RECEIVED
3 RT-to-RT GAP / SYNCH / ADDRESS ERROR
2 RT-to-RT NO RESPONSE ERROR
1 RT-to-RT 2ND COMMAND WORD ERROR
0(LSB) COMMAND WORD CONTENTS ERROR
TABLE 18. BC FRAME TIME / RT LAST COMMAND /
MT TRIGGER REGISTER (READ/WRITE 0DH)
BIT DESCRIPTION
TABLE 21. CONFIGURATION REGISTER #6
(READ/WRITE 18H)
BIT DESCRIPTION
15(MSB) BIT 15
15(MSB) ENHANCED BUS CONTROLLER
••
14 ENHANCED CPU ACCESS
0(LSB)
BIT 0
13
COMMAND STACK POINTER INCREMENT ON EOM
(RT, MT)
12 GLOBAL CIRCULAR BUFFER ENABLE
11 GLOBAL CIRCULAR BUFFER SIZE 2
TABLE 19. RT STATUS WORD REGISTER
(READ/WRITE 0EH)
BIT DESCRIPTION
15(MSB) LOGIC “0”
14 LOGIC “0”
13 LOGIC “0”
12 LOGIC “0”
11 LOGIC “0”
10 MESSAGE ERROR
9 INSTRUMENTATION
8 SERVICE REQUEST
7 RESERVED
6 RESERVED
10
9
8
7
6
5
4
3
2
1
0(LSB)
GLOBAL CIRCULAR BUFFER SIZE 1
GLOBAL CIRCULAR BUFFER SIZE 0
DISABLE INVALID MESSAGES TO INTERRUPT STATUS
QUEUE
DISABLE VALID MESSAGES TO INTERRUPT STATUS
QUEUE
INTERRUPT STATUS QUEUE ENABLE
RT ADDRESS SOURCE
ENHANCED MESSAGE MONITOR
RESERVED
64-WORD REGISTER SPACE
CLOCK SELECT 1
CLOCK SELECT 0
5 RESERVED
4 BROADCAST COMMAND RECEIVED
3 BUSY
2 SSFLAG
1 DYNAMIC BUS CONTROL ACCEPT
0(LSB) TERMINAL FLAG
Data Device Corporation
BU-6174X/6184X/6186X
www.ddc-web.com
11
M-12/04-0

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