PDF VSC880 Data sheet ( Hoja de datos )

Número de pieza	VSC880
Descripción	High Performance 16 x 16 Serial Crosspoint Switch
Fabricantes	Vitesse Semiconductor
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VSC880 eet4U.coVm ITESSEData Sheet SEMICONDUCTOR CORPORATION High Performance 16x16 Serial Crosspoint Switch taShFeatures a• 16x16 Synchronous Serial Crosspoint Switch .D• Serial Data Rates: 2.0Gb/s w • 32Gb/s Aggregate Data Bandwidth ww • Parallel Switches Can Increase Data Bandwidth in Multiples of 32Gb/s m• Designed in Conjunction with the VSC870 oBackplane Transceiver .c• Automatic Word and Cell Synchronization to the Transceiver U• Two Modes of Operation: Distributed Control t4Self-routing Packet Mode and Central Control Cell Mode e• Multicast Supported in All Modes • Supports Variable Length Packets in Packet Mode • Built-in Flow Control Channel in Packet Mode • Supports Cell Synchronization in Cell Mode • Parallel CPU Interface and Parallel Switch Configuration Interface • Loopback, Built-in Self Test and Scan Functions • 5V Tolerant TTL Inputs • Dual 3.3V/2.5V or Dual 3.3V/2.0V Power Supplies • Serial Port Quadrants Can be Powered Down • Available in 304 BGA Package eVSC880 Block Diagram taShTXS+/TXS- Serial Port (16x) Parallel to Serial .DaRXS+/RXS- wWCLK wREFCLK TCLKEN w omLOCKDET .cCCLK t4URESET BSTLPBK eeBSTEN hBSTRST SBSTPASS DRU Serial to Parallel CMU Clock Gen BIST Logic Port Logic Switch Matrix Arbitration Logic and Switch Control Registers VSCTE VSCIPNC VSCOPNC MEN FACLPBK CMODE TESTEN SCANIN SCANOUT CEN DATA[15:0] FI[3:0] WEN Status and Control Registers ADDR[5:0] CDATA[7:0] CWEN CSEL INT RESYNEN ww.DataG52191-0, Rev 4.2 w01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Page 1 Internet: www.vitesse.com 1 page VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC880 High Performance 16x16 Serial Crosspoint Switch 1.1.2 Data Scrambling To allow the VSC870 CRU to recover the bit clock, a 15% edge transition density must be guaranteed on the serial data links. All command words and connection request words contain this required density. In order to get this density on data words, scrambling must be employed by the transceiver (see VSC870 data sheet). 1.1.3 Bit Synchronization In Packet Mode and Cell Mode, the switch acts as the source of the bit clock. It multiplies the local 62.5MHz reference clock by 34 to generate a 2.125GHz clock and uses this clock to serialize the 32-bit word and 2 overhead bits. The transceiver receives and feeds this serial data stream to a digital CRU to recover the bit clock and deserialize the data stream to a 32-bit word plus 2 overhead bits at 62.5MHz. The transceiver also uses this recovered clock to serialize its transmit words that are sent to the switch. In this way, the switch and all the transceivers are frequency-locked to one clock source which is provided by the reference clock on the switch card. Because of this, the switch chip needs to recover only the phase information on the serial receive channel using a data recovery unit (DRU). The DRU is designed as a delay lock loop and remains phase-locked to the incoming data stream as long as the temperature does not change by more than 20°C after link initialization. If this temperature variation is exceeded, a link error may occur causing the link to reinitialize. Because of this, system reset should be held until the system reaches temperature stability before starting the link initializing process. 1.1.4 Word Synchronization During power up or at reset, the transceiver can initiate the word synchronization process. First, the transceiver sends reset patterns to the switch to request that the switch starts the initialization process. The switch, upon receiving this request, will send out special ALIGN words. The transceiver receives this serial data stream and word aligns to this ALIGN word by adjusting its own word boundary one bit at a time. Upon detecting the correct word alignment, it starts the transmit word alignment process. In this process, the transceiver continuously sends ALIGN words to the switch. The switch uses its own word clock (REFCLK) to detect this ALIGN word. If the transmitters word is not aligned to the switch chip word clock when it arrives at the switch, the switch chip continues to send out ALIGN words. After receiving 32 ALIGN words from the switch chip, the transceiver changes its transmit word boundary by 1 bit position and repeats the process (this limits the distance from the transceiver to the switch to less than 180ns one way). If the switch detects the transceivers ALIGN word correctly, it sends IDLE words to the transceiver to signal that the transmitter has now word synchronized with the switch. It also clears the internal registers LERR, TERR, DERR and CERR and sets the signal INT HIGH if all the enabled serial channels are successfully initialized (see section 1.4). 1.1.5 Cell Synchronization If CMODE is set HIGH, after the word synchronization process completes, the transceiver starts the cell synchronization process. In this process, the transceiver detects the received cell clock (CCLK) sent from the switch embedded in the alignment word. The switch delays the global cell clock to adjust out the pipeline delay from the transceiver to the switch. The switch chip does this by connecting each port to itself during link initialization. By sending an ALIGN words to itself, the transceiver can adjust the transmit clock until it is properly phase shifted relative to the global cell clock. If cells are sent from the transceiver aligned to this transmit cell clock, they will arrive at the switch aligned to the master cell clock which is originated at the switch. For this alignment process to work, the minimum cell size is 8 words (32 bytes). G52191-0, Rev 4.2 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 5 5 Page Data Sheet VSC880 VITESSE SEMICONDUCTOR CORPORATION High Performance 16x16 Serial Crosspoint Switch Figure 4: Switch Configuration Interface Functional Timing (CEN=0) REFCLK FI[3:0] DATA[15:0] WEN CCLK F0 F1 F2 F3 C0 C1 C2 C3 Switch updated in this cycle Min. of 5 Cycles The switch configuration data for each port is as follows: F0[3:0] = FI[port9], FI[port8], FI[port1], FI[port0] F1[3:0] = FI[port11], FI[port10], FI[port3], FI[port2] F2[3:0] = FI[port13], FI[port12], FI[port5], FI[port4] F3[3:0] = FI[port15], FI[port14], FI[port7], FI[port6] C0[15:0] = Port9[3:0], Port8[3:0], Port1[3:0], Port0[3:0] C1[15:0] = Port11[3:0], Port10[3:0], Port3[3:0], Port2[3:0] C2[15:0] = Port13[3:0], Port12[3:0], Port5[3:0], Port4[3:0] C3[15:0] = Port15[3:0], Port14[3:0], Port7[3:0], Port6[3:0] Where FI[portN] is the Force IDLE bit for port N and PortN[3:0] is the input port number to be connected to output port N. 1.7 Built-in Self-Test The switch has built-in self-test logic that can be used to verify the high-speed circuitry as well as the switch matrix while operating at full speed. The built-in self-test mode is enabled by setting the built-in self-test enable (BSTEN) signal HIGH. If the signal BSTLPBK is set HIGH and TESTEN is set LOW, it loops all 16 serial outputs back to the Data Recovery Unit (DRU) at the serial inputs. An internal Pseudo Random Bit Sequence (PRBS) generator connected to the switch matrix at port 0. The random data is sent to port 0, passed through the switch matrix, looped back through the serial interface and returned to the data comparator. If this data matches the correct pattern, BSTPASS is set HIGH. By configuring port 0 to connect to other ports (ports 1 through 15) through the switch matrix using the parallel configuration interface, the rest of the serial channels (one port at a time) can be tested in turn. For example, port 0 can be connected to port 1 by configuring the switch matrix. The PRBS generator transmits the random data through port 0 to port 1, and the random data is then looped back from port 1 to port 0 and the data comparator. To test all 16 ports, the user will need to configure the switch matrix 16 times to test all ports. G52191-0, Rev 4.2 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 11 11 Page

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