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PDF TC203Gxxxx Data sheet ( Hoja de datos )

Número de pieza TC203Gxxxx
Descripción CMOS ASIC Family
Fabricantes Toshiba 
Logotipo Toshiba Logotipo



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No Preview Available ! TC203Gxxxx Hoja de datos, Descripción, Manual

TOSHIBAeet4U.com TACSI2C03FaSmeriileys CMOS0.4µm, Mixed 3.3/5.0V I/O
taShThe TC203 series is a high speed, high density 0.4µm
aCMOS Family of ASICs for mixed 3/5V operation.
w.DBenefits
w– True, no compromise, mixed 3/5V operation
w- Achieved by technology, not by circuit compromise
m- Inexpensive extra technology step
- No restrictions in 3V or 5V I/O buffer placement
o– True 3.3V, 0.4µm CMOS technology
.c- Process optimized for 3.3V operation
- No external components required
- Full performance core with full 3.3V and 5V drive I/O
U- Typical loaded gate delay = 230ps
t4- 690K usable gates
– Low power
- 20% less than 0.5µm ASICs
e– Advanced packaging
e- HQFP, BGA
- High density pad option for pad limited designs
h• 62µm inner lead TAB
– New accurate delay model with commercial sign-off
S– A Toshiba System ASIC product
ataGate Array Master Lineup
.DReference
Usable Gates
Double Layer Metal Triple Layer Metal
wTC203G02/52
TC203G04/54
wTC203G06.56
w mTC203G08/58
.coTC203G10/60
UTC203G12/62
t4TC203G14/64
eTC203G16/66
eTC203G20/70
ShTC203G24/74
taTC203G32/82
aTC203G36/86
.DTC203G40/90
wTC203G42/92
11K
20K
29K
37K
44K
54K
64K
78K
95K
122K
171K
224K
284K
398K
20K
35K
50K
64K
77K
94K
112K
137K
165K
211K
300K
390K
494K
694K
wwNote: DLM=Double Layer Metal, TLM=Triple Layer Metal
Features
– Macrocell libray contains both normal and low power basic
macrocells ie:
Cell Type
Delay
Power
Low-powertype*
Normaltype
290ps*
190ps*
2.80µW/MHz/gate
3.55µW/MHz/gate
* 2-input NAND, fanout=2 plus typical interconnect load
– Multilevel 5V/3V I/O buffers
– Over 450 I/O cells including high drive (upto 24mA), slew rate
control, and high speed output buffers
– Compiled cells including asynchronous and synchronous
RAM, single and dual port RAM and ROM
– Hard macrocells including those for PCI bus interface are
available. Some fast multipliers, adders, ALUs, UARTs timers
and special I/O cells are in development.
– Supports R3900 MIPS processor core
ASIC Methodologies Support
– Gate array: 14 master sizes
– Embedded array and Standard cell: 30 master sizes
Wirebond Pads
80
104
128
144
160
176
192
208
240
272
336
384
432
512
I/O Pads
TAB 62µm
152
200
248
288
316
348
380
420
-
-
-
-
-
-
TAB 83µm
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Preliminary
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
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