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PDF GLT41016 Data sheet ( Hoja de datos )
| Número de pieza | GLT41016 | |
| Descripción | 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT | |
| Fabricantes | G-Link Technology | |
| Logotipo |  |
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GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Feb 2004 (Rev 2.2)
ataSheeFeatures :
w.D∗ 65,536 words by 16 bits organization.
w∗ Fast access time and cycle time.
w∗ Dual CAS Input.
∗ Low power dissipation.
m∗ Read-Modify-Write, RAS -Only Refresh,
CAS -Before- RAS Refresh, Hidden
oRefresh and Test Mode Capability.
.c∗ 256 refresh cycles per 4ms.
∗ Available in 40-pin 400 mil SOJ and 40/44
pin TSOP (II).
U∗ Single 5.0V±10% Power Supply.
t4∗ All inputs and Outputs are TTL
compatible.
e∗ Extended Data-Out(EDO) Page Mode
operation.
Description :
The GLT41016 is a 65,536 x 16 bit high-
performance CMOS dynamic random access
memory. The GLT41016 offers Fast Page
mode with Extended Data Output, and has
both BYTE WRITE and WORD WRITE
access cycles via two CAS pins. The
GLT41016 accepts 256-cycle refresh in 4ms
interval.
All inputs are TTL compatible. EDO
Page Mode operation allows random access
up to 256 x 16 bits, within a page, with cycle
times as short as 12ns.
The GLT41016 is best suited for
graphics, and DSP applications requiring
high performance memories.
ataSheHIGH PERFORMANCE
.DMax. RAS Access Time, (tRAC)
wMax. Column Address Access Time, (tAA)
Min. Extended Data Out Page Mode Cycle Time, (tPC)
wwMin. Read/Write Cycle Time, (tRC)
30
30 ns
15 ns
12 ns
65 ns
35
35 ns
18 ns
13 ns
70 ns
40
40 ns
20 ns
15 ns
75 ns
45
45 ns
22 ns
18 ns
80 ns
mMax. CAS Access Time (tCAC)
10 ns
11 ns 12 ns
12 ns
Sheet4U.coG-Link Technology Corporation,Taiwan
taWeb : www.glink.com.tw Email : [email protected]
aTEL : 886-2-27968078
www.D- 1 -
1 page  
G-LINK
GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Feb 2004 (Rev 2.2)
Truth Table: GLT41016
Function
Standby
Read: Word
Read: Lower Byte
RAS
H
L
L
CASL CASH
H→X H→X
LL
LH
WE
X
H
H
Read: Upper Byte
L HLH
Write: Word(Early Write) L
LLL
OE ADDRESS
DQs
X High-Z
Notes
L ROW/COL Data Out
L ROW/COL Lower Byte,Data-
Out
Upper Byte,High-Z
L ROW/COL Lower Byte,High-Z
Upper Byte,Data-
Out
X ROW/COL Data-In
Write: Lower Byte (Early)
Write: Upper Byte (Early)
Read Write
EDO-Page-
Mode Read
1st Cycle
2nd Cycle
L
L
L
L
L
L
H
L
H→L
H→L
H
L
L
H→L
H→L
L
L
H→L
H
H
X
X
L→H
L
L
ROW/COL Lower Byte,Data-In
Upper Byte,High-Z
ROW/COL Lower Byte,High-Z
Upper Byte,Data-In
ROW/COL Data-Out,Data-In
ROW/COL Data-Out
COL Data-Out
1,2
1
1
EDO-Page- 1st Cycle L H→L H→L L
Mode Write 2nd Cycle L H→L H→L L
X ROW/COL Data-In
X COL Data-In
2
2
EDO-Page- 1st Cycle
L
H→L H→L H→L L→H ROW/COL Data-Out,Data-In
1,2
Mode Read-
Write
2nd Cycle L H→L H→L H→L L→H COL Data-Out,Data-In 1,2
Hidden
Read L→H→L L L H L ROW/COL Data-Out
Refresh
Write L→H→L L L L X ROW/COL Data-In
RAS -Only Refresh
L H H X X ROW High-Z
CBR Refresh
H→L
L
L
X
X
High-Z
1
2,3
4
Notes:
1. These READ cycles may also be BYTE READ cycles (either UCAS or LCAS active).
2. These WRITE cycles may also be BYTE READ cycles (either UCAS or LCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active ( UCAS or LCAS ).
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : [email protected]
TEL : 886-2-27968078
-5-
5 Page 
G-LINK
Early Write Cycle
NOTE : DOUT = OPEN
GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Feb 2004 (Rev 2.2)
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : [email protected]
TEL : 886-2-27968078
- 11 -
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