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PDF PCI6154 Data sheet ( Hoja de datos )
| Número de pieza | PCI6154 | |
| Descripción | PCI to PCI Bridge | |
| Fabricantes | PLX Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PCI6154 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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www.DataSheet4U.com
.comPCI 6154 (HB2)
PCI-to-PCI Bridge
t4UData Book
www.DataShee www.DataSheet4U.com
1 page  
PCI 6154 PCI-to-PCI Bridge
Adaptive High Performance Asynchronous 66 MHz 64-bit PCI-to-PCI Bridge for
Servers, Storage, Telecommunication, Networking- and Embedded Applications
PLX's latest PCI 6154 64-bit PCI-to-PCI bridge is designed for high performance, high availability applications in
bus expansions, programmable data transfer rate control, frequency conversions from slower PCI to faster PCI or
from faster PCI to slower PCI buses. PCI 6154 has sophisticated buffer management and buffer configuration
options designed to provide customizable performance optimization.
• PCI Local Bus Specification Rev 2.3
support
• High speed PCI buffer supports 3.3V
signaling with 5V input signal tolerance
• Asynchronous design supports standard
66MHz to 33MHz and faster secondary port
speed such as 33MHz to 40/50/60/66MHz
conversion
• Programmable Address Translation to
Secondary Bus
• Flow-Through 0 wait state burst up to 4K
bytes for optimal large volume data transfer
• Supports up to 4 simultaneous posted write
transactions and 4 simultaneous Delayed
transactions in each direction
• Provides 1K Bytes of buffering
! 256 byte upstream posted write
buffer
! 256 byte downstream posted write
buffer
! 256 byte upstream read data buffer
! 256 byte downstream read data
buffer
• Programmable prefetch amount of up to 256
bytes for maximum read performance
optimization
• Supports out of order delayed transactions
• Serial EEPROM loadable and
programmable PCI READ ONLY Register
configurations.
• External arbiter or programmable arbitration
for 9 bus masters on secondary interface
support
• 10 Secondary clock outputs with pin
controlled enable and individual maskable
control
• PCI Mobile Design Guide and Power
Management D3 Cold Wakeup capable
• 4 GPIO pins with output control
• Enhanced address decoding
! Support 32-bit I/O address range
! 32-bit memory-mapped I/O address
range
! ISA aware mode for legacy support in
the first 64KB of I/O address range
! VGA addressing and palette snooping
support
• Provides an IEEE standard 1149.1 JTAG
interface for boundary scan test
• PCI 6154 uses Industry standard 31mm x
31mm 304 ball PBGA package
PCI 6154 Data Book v2.0
2003 PLX Technology, Inc. All rights reserved.
5
5 Page 
1 Register Index
When looking up registers, please also check registers below preceded with “Primary” or “Secondary”.
Arbiter Control Register .............................................................35
Bridge Control Register .............................................................33
Cache Line Size Register ..........................................................30
Capability Identifier
Non-transparent, Primary .......................................... 50, 51, 52
Chip Control Register
Non-transparent, Primary ......................................................34
Class Code Register..................................................................30
Device ID Register.....................................................................29
Diagnostic Control Register .......................................................34
ECP Pointer...............................................................................32
EEPROM Address.....................................................................44
EEPROM Control ................................................................43, 44
GPIO Input Data Register ..........................................................46
GPIO Output Data Register .......................................................46
GPIO Output Enable Register....................................................46
Header Type Register................................................................30
Hot Swap Register
Non-transparent, Primary ......................................................51
Hot Swap Switch
Non-transparent, Primary ......................................................49
I/O Base Address Upper 16 Bits Register ..................................32
I/O Base Register ......................................................................31
I/O Limit Address Upper 16 Bits Register...................................32
I/O Limit Register.......................................................................31
Internal Arbiter Control Register.................................................42
Interrupt Pin Register.................................................................32
Memory Base Register ..............................................................32
Memory Limit Register...............................................................32
Miscellaneous Options...............................................................37
Next Item Pointer
Non-transparent, Primary .......................................... 50, 51, 52
P_SERR_L Event Disable Register ...........................................45
P_SERR_L Status Register .......................................................48
PMCSR Bridge Support
Non-transparent, Primary...................................................... 51
Power Management Capabilities
Non-transparent, Primary...................................................... 50
Power Management Control/ Status
Non-transparent, Primary...................................................... 51
Prefetchable Memory Base Register ......................................... 32
Prefetchable Memory Base Register Upper 32 Bits ................... 32
Prefetchable Memory Limit Register.......................................... 32
Prefetchable Memory Limit Register Upper 32 Bits ................... 32
Primary Bus Number Register................................................... 30
Primary Command Register ...................................................... 29
Primary Flow Through Control Register..................................... 35
Primary Latency Timer Register ................................................ 30
Primary Side Incremental Prefetch Count.................................. 39
Primary Side Maximum Prefetch Count..................................... 40
Primary Side Prefetch Line Count ............................................. 39
Primary Status Register ............................................................ 30
Revision ID Register.................................................................. 30
Secondary Bus Number Register .............................................. 30
Secondary Clock Control Register............................................. 47
Secondary Flow Through Control Register ................................ 41
Secondary Latency Timer.......................................................... 31
Secondary Side Incremental Prefetch Count ............................. 40
Secondary Side Maximum Prefetch Count ................................ 40
Secondary Side Prefetch Line Count......................................... 39
Secondary Status Register........................................................ 31
Subordinate Bus Number Register ............................................ 31
Timeout Control Register.......................................................... 36
Vendor ID Register.................................................................... 29
VPD Data Register
Non-transparent, Primary...................................................... 52
VPD Register
Non-transparent, Primary...................................................... 52
PCI 6154 Data Book v2.0
2003 PLX Technology, Inc. All rights reserved.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PCI6154.PDF ] | |
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