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PDF UPD44164084 Data sheet ( Hoja de datos )

Número de pieza UPD44164084
Descripción (UPD44164084/184/364) 18M-BIT DDRII SRAM 4-WORD BURST OPERATION
Fabricantes NEC 
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD44164084, 44164184, 44164364
18M-BIT DDRII SRAM
4-WORD BURST OPERATION
Description
The µPD44164084 is a 2,097,152-word by 8-bit, the µPD44164184 is a 1,048,576-word by 18-bit and the
µPD44164364 is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell.
The µPD44164084, µPD44164184 and µPD44164364 integrates unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and
/K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
1.8 ± 0.1 V power supply and HSTL I/O
DLL circuitry for wide output data valid window and future frequency scaling
Pipelined double data rate operation
Common data input/output bus
Four-tick burst for reduced address frequency
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output clocks (C and /C) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability with µs restart
User programmable impedance output
Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz), 6.0 ns (167 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15822EJ7V1DS00 (7th edition)
Date Published July 2004 NS CP(K)
Printed in Japan
The mark shows major revised points.
2001

1 page




UPD44164084 pdf
µPD44164084, 44164184, 44164364
165-pin PLASTIC BGA (13 x 15)
(Top View)
[µPD44164364F5-EQ1]
1 2 3 4 5 6 7 8 9 10 11
A /CQ VSS NC R, /W /BW2 /K /BW1 /LD A VSS CQ
B NC DQ27 DQ18 A /BW3 K /BW0 A
NC NC DQ8
C NC
NC DQ28 VSS
A
A0 A1 VSS NC DQ17 DQ7
D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16
E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6
F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5
G NC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14
H /DLL
VREF
VDDQ VDDQ
VDD
VSS
VDD
VDDQ VDDQ
VREF
ZQ
J NC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4
K NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3
L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2
M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1
N NC DQ35 DQ25 VSS
A
A
A VSS NC NC DQ10
P NC
NC DQ26 A
A
C
A
A NC DQ9 DQ0
R TDO TCK
A
A
A /C
A
A
A TMS TDI
A0, A1, A
DQ0 to DQ35
/LD
R, /W
/BW0 to /BW3
K, /K
C, /C
CQ, /CQ
ZQ
/DLL
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
Remark Refer to Package Drawing for the index mark.
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Data Sheet M15822EJ7V1DS
5

5 Page





UPD44164084 arduino
Electrical Specifications
µPD44164084, 44164184, 44164364
Absolute Maximum Ratings
Parameter
Supply voltage
Output supply voltage
Input voltage
Input / Output voltage
Operating ambient temperature
Storage temperature
Symbol Conditions
VDD
VDDQ
VIN
VI/O
TA
Tstg
MIN.
–0.5
–0.5
–0.5
–0.5
0
–55
TYP.
MAX.
+2.9
VDD
VDD + 0.5 (2.9 V MAX.)
VDDQ + 0.5 (2.9 V MAX.)
70
+125
Unit
V
V
V
V
°C
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70 °C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit Note
Supply voltage
VDD 1.7 1.9 V
Output supply voltage
VDDQ
1.4
VDD
V1
High level input voltage
VIH (DC)
VREF + 0.1
VDDQ + 0.3 V
1, 2
Low level input voltage
VIL (DC)
–0.3
VREF – 0.1 V 1, 2
Clock input voltage
VIN
–0.3
VDDQ + 0.3 V
1, 2
Reference voltage
VREF
0.68
0.95 V
Notes 1. During normal operation, VDDQ must not exceed VDD.
2. Power-up: VIH VDDQ + 0.3 V and VDD 1.7 V and VDDQ 1.4 V for t 200 ms
Recommended AC Operating Conditions (TA = 0 to 70 °C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit Note
High level input voltage
VIH (AC)
VREF + 0.2
– V1
Low level input voltage
VIL (AC)
VREF – 0.2
V
1
Note 1. Overshoot: VIH (AC) VDD + 0.7 V for t TKHKH/2
Undershoot: VIL (AC) – 0.5 V for t TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
Data Sheet M15822EJ7V1DS
11

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