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PDF IDT79RC64V475 Data sheet ( Hoja de datos )

Número de pieza IDT79RC64V475
Descripción (IDT79RC64V474 / IDT79RC64V475) 64-Bit Microprocessor
Fabricantes IDT 
Logotipo IDT Logotipo



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No Preview Available ! IDT79RC64V475 Hoja de datos, Descripción, Manual

.comRISControllerTM Embedded
U 64-bit Microprocessor, based on
et4 RISCore4000TM
RC64474
RC64475
SheFeatures
tax High performance 64-bit microprocessor, based on the
aRISCore4000
.D– Minimized branch and load delays, through streamlined
5-stage scalar pipeline.
w– Single and double precision floating-point unit
w– 125 peak MFLOP/s at 250 MHz
w – 330 Dhrystone MIPS at 250 MHz
m– Flexible RC4700-compatible MMU
– Joint TLB on-chip, for virtual-to-physical address mapping
ox On-chip two-way set associative caches
.c– 16KB instruction cache (I-cache)
– 16KB data cache (D-cache)
x Optional I-cache and D-cache locking (per set), provides
Uimproved real-time support
x Enhanced, flexible bus interface allows simple, low-cost
t4design
– 64-bit Bus Interface option, 1000MB/s bandwidth support
e– 32-bit Bus Interface option, 500MB/s bandwidth support
– SDRAM timing protocol, through delayed data in write cycles
e– RC4000/RC5000 family bus-protocol compatibility
– Bus runs at fraction of pipeline clock (1/2 to 1/8)
hx Implements MIPS-III Instruction Set Architecture (ISA)
x 3.3V core with 3.3V I/O
x Software compatible with entire RISController Series of
Embedded Microprocessors
x Industrial temperature range support
x Active power management
– Powers down inactive units, through sleep-mode feature
x 100% pin compatibility between RC64574, RC64474 and
RC4640
x 100% pin compatibility between RC64575, RC64475 and
RC4650
x RC64474 available in 128-pin QFP package, for 32-bit only
systems
x RC64475 available in 208-pin QFP package, for full 64/32 bit
systems
x Simplified board-level testing, through full Joint Test Action
Group (JTAG) boundary scan
x Windows® CE compliant
taSBlock diagram
a330 MIPS
.D64-bit
RISCore4000
wCPU Core
System Control
Coprocessor
(CPO)
125 MFLOPS
Single/Double
Precision
FPA
w Control Bus
w .comInstruction Bus
t4U16KB
eInstruction Cache
She(Lockable)
Data Bus
32-/64-bit
Synchronized
System
Interface
16KB
Data Cache
(Lockable)
.DataThe IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trade-
marks of Integrated Device Technology, Inc.
www1 of 25
April 10, 2001
2001 Integrated Device Technology, Inc.
DSC 4952

1 page




IDT79RC64V475 pdf
RC64474™ RC64475™
Serial
Bit
Description
Value & Mode Setting
255:18
17:15
14:13
12
11
10:9
7:5
8
4:1
0
Reserved
Must be 0
WAdrWData_Del
Write address to write data delay in Master-
Clock cycles.®
000 0 cycles
001 1 cycle
010 2 cycles
011 3 cycles
100 4 cycles
101 5 cycles
110 6 cycles
111 7 cycles
Drv_Out
output driver slew rate control. Bit 14 is MSB.
Affects only non-clock outputs.
Output driver strength:
10 100% strength (fastest)
11 83% strength
00 67% strength
01 50% strength (slowest)
System interface bus width
0 64-bit system interface
1 32-bit system interface
TmrIntEn
Disables the timer interrupt on Int*[5]
0 Enabled Timer Interrupt
1 Disabled Timer Interrupt
Non-block write
Selects non-block write type. Bit 10 is MSB.
00 RC4x00 compatible
01 Reserved
10 Pipelined writes
11 Write re-issue
Clock
Multiplier
MasterClock is multiplied internally to gener-
ate PClock
Clock multiplier:
0 Multiply by 2
1 Multiply by 3
2 Multiply by 4
3 Multiply by 5
4 Multiply by 6
5 Multiply by 7
6 Multiply by 8
7 Reserved
EndBit
Specifies byte ordering
0 Little endian
1 Big endian
Writeback data rate
System interface data rate for block writes
only: bit 4 is MSB
64-bit:
9:15 Reserved
8 dxxxdxxxdxxxdxxx
7 ddxxxxxxddxxxxxx
6 dxxdxxdxxdxx
5 ddxxxxddxxxx
4 ddxxxddxxx
3 dxdxdxdx
2 ddxxddxx
1 ddxddx
0 dddd
Reserved
Must be zero
32-bit:
9:15 Reserved
8 wxxxwxxxwxxxwxxxwxxxwxxxwxxxwxxx
7 wwxxxxxxwwxxxxxxwwxxxxxxwwxxxxxx
6 wxxwxxwxxwxxwxxwxxwxxwxx
5 wwxxxxwwxxxxwwxxxxwwxxxx
4 wwxxxwwxxxwwxxxwwxxx
3 wxwxwxwxwxwxwxwx
2 wwxxwwxxwwxxwwxx
1 wwxwwxwwxwwx
0 Æ wwwwwwww
Table 3 Boot-time Mode Stream
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April 10, 2001

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IDT79RC64V475 arduino
RC64474™ RC64475™
Pin
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Function
SysCmd3
VSS
Vcc
SysAD38
SysAD6
ModeClock
WrRdy*
SysAD37
SysAD5
VSS
Vcc
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
Pin Function Pin Function Pin
86 Vcc
87 SysAD17
88 SysAD49
89 Int0*
90 SysAD18
91 VSS
92 Vcc
93 SysAD50
94 ValidIn*
95 SysAD19
96 SysAD51
97 VSS
98 Vcc
99 ValidOut*
100 SysAD20
101 N.C.
102 N.C.
103 N.C.
104 N.C.
138 SysAD25
139 SysAD57
140 N.C.
141 VSS
142 N.C
143 SysAD26
144 SysAD58
145 N.C.
146 Vcc
147 VSS
148 SysAD27
149 N.C.
150 JR_Vcc
151 N.C.
152 N.C.
153 N.C.
154 N.C.
155 N.C.
156 N.C.
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Table 6 RC64475 208-pin QFP Package Pin-Out (Page 2 of 2)
Function
SysADC5
SysADC1
Vcc
VSS
SysAD47
SysAD15
SysAD46
Vcc
VSS
SysAD14
SysAD45
SysAD13
SysAD44
VSS
Vcc
SysAD12
SysCmdP
SysAD43
N.C.
RC64474 128-pin QFP Package Pin-out
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
Function
JTAG32*
SysCmd2
Vcc
Vss
SysAD5
WrRdy*
ModeClock
SysAD6
Vcc
Vss
SysCmd3
SysAd7
SysCmd4
Pin Function Pin Function Pin
33 Vcc
34 Vss
35 SysAD13
36 SysAD14
37 Vss
38 Vcc
39 SysAD15
40 Vss
41 Vcc
42 SysADC1
43 Vss
44 Vcc
45 MasterClock
65 Vcc
66 SysAD28
67 ColdReset*
68 SysAD27
69 Vss
70 Vcc
71 JR_Vcc
72 SysAD26
73 N.C.
74 Vss
75 N.C.
76 SysAD25
77 Vss
97
98
99
100
101
102
103
104
105
106
107
108
109
Table 7 RC64474 128-pin QFP Package Pin-out (Page 1 of 2)
Function
Vcc
Vss
SysAD19
ValidIn*
Vcc
Vss
SysAD18
Int0*
SysAD17
Vcc
Vss
Int1*
SysAD16
11 of 25
April 10, 2001

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