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PDF S21152BB Data sheet ( Hoja de datos )
| Número de pieza | S21152BB | |
| Descripción | PCI to PCI Bridge | |
| Fabricantes | Intel | |
| Logotipo |  |
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21e1t45U2.cPomCI-to-PCI BridgeDatasheet
ataSheProduct Features
w.D ■ Complies fully with Revision 2.1 of the PCI
w Local Bus Specification,
w ■ Complies fully with Revision 1.1 of the
PCI-to-PCI Bridge Architecture
mSpecification,
■ Complies fully with the Advanced
oConfiguration Power Interface (ACPI)
Specification
.c■ Complies fully with the PCI Power
Management Specification, Revision 1.01
U■ Implements delayed transactions for all PCI
configuration, I/O, and memory read
t4commands—up to three transactions
simultaneously in each direction
■ Allows 88 bytes of buffering (data and
eaddress) for posted memory write
commands in each direction—up to three
etransactions simultaneously in each
direction
h■ Allows 72 bytes of read data buffering in
each direction
S■ Provides concurrent primary and secondary
bus operation to isolate traffic
ta■ Provides five secondary clock outputs
— Low skew, permitting direct drive of
aoption slots
— Individual clock control through
.Dconfiguration space
■ Provides arbitration support for four
secondary bus devices
— A programmable 2-level arbiter
— Hardware disable control, permitting use
of an external arbiter
■ Provides enhanced address decoding
— A 32-bit I/O address range
— A 32-bit memory-mapped I/O address
range
— A 64-bit prefetchable memory address
range
— ISA-aware mode for legacy support in
the first 64 KB of I/O address range
— VGA addressing and VGA palette
snooping support
■ Supports PCI transaction forwarding for the
following commands
— All I/O and memory commands
— Type 1 to Type 1 configuration
commands
— Type 1 to Type 0 configuration
commands (downstream only)
— All Type 1 to special cycle configuration
commands
■ Includes downstream lock support
■ Supports both 5 V and 3.3 V signaling
environments
w1. 21152–AB and later revisions only. The 21152–AA does not implement this feature.
ww .DataSheet4U.comOrder Number: 278060, Revision: 002US
www April 2005
1 page  
Shortened Product Name
40 Configuration Register Values After Reset ...............................................................................141
Datasheet
21152 PCI-to-PCI Bridge
Order Number: 278060, Revision: 002US
April 2005
5
5 Page 
21152 PCI-to-PCI Bridge
Figure 4.
21152 Downstream Data Path
Delayed
Transaction
Queue
p_ad Posted Write Data Queue
Address
Control
s_ad
1.2.1
1.2.2
1.2.3
Delayed Read Data Queue
LJ-04634.AI4
Posted Write Queue
The posted write queue contains the address and data of memory write transactions targeted for the
opposite interface. The posted write transaction can consist of an arbitrary number of data phases,
subject to the amount of space in the queue and disconnect boundaries. The posted write queue can
contain multiple posted write transactions. The number of posted write transactions that can be
queued at one time is dependent upon their burst size. The posted write queue consists of 88 bytes
in each direction.
Delayed Transaction Queue
For a delayed write request transaction, the delayed transaction queue contains the address, bus
command, 1 Dword of write data, byte enable bits, and parity. When the delayed write transaction
is completed on the target bus, the write completion status is added to the corresponding entry.
For a delayed read request transaction, the delayed transaction queue contains the address and bus
command, and for nonprefetchable read transactions, the byte enable bits. When the delayed read
transaction is completed on the target bus, the read completion status corresponding to that
transaction is added to the delayed request entry. Read data is placed in the read data queue.
The delayed transaction queue can hold up to three transactions (any combination of read and write
transactions).
Read Data Queue
The read data queue contains read data transferred from the target during a delayed read
completion. Read data travels in the opposite direction of the transaction. The primary-to-
secondary read data queue contains read data corresponding to a delayed read transaction residing
in the secondary-to-primary delayed transaction queue. The secondary-to-primary read data queue
contains read data corresponding to a delayed read transaction in the primary-to-secondary delayed
transaction queue. The amount of read data per transaction depends on the amount of space in the
queue and disconnect boundaries.
Read data for up to three transactions, subject to the burst size of the read transactions and available
queue space, can be stored. The read data queue for the 21152 consists of 72 bytes in each
direction.
Datasheet
21152 PCI-to-PCI Bridge
Order Number: 278060, Revision: 002US
April 2005
11
11 Page | ||
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