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Número de pieza | CA91C142 | |
Descripción | Debug and Initialization Notes | |
Fabricantes | Tundra | |
Logotipo | ||
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mDebug and Initialization Notes
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1 page 1
1. Universe II (CA91C142) Debug and
Initialization Notes
This application note is intended to show common problems that may occur which can
cause the Universe II not to operate as expected. The sections addressed in this design
note include:
• “Hardware” on page 1
• “Software and Registers” on page 8
• “Registers” on page 10
• “Generating PCI Configuration Cycles” on page 13
1.1
Overview
This application note is intended to show common problems that may occur
whichwould cause the Universe II not to operate as expected. This application note is
intended to be used as a guide only.
This document isdivided into two sections Hardware and Software. Each section
outlines various issues within those areas which would cause the Universe II to not
function as expected. As a reference, users may also wish to read the application note on
Fast Initialization. (8091142_AN003_xx)
Note
All references to the Universe II manual refer to the Spring 1998
version (8091142.MD300.01).
1.2 Hardware
The following describes various hardware issues associated with the Universe II.
8091142_AN005_01
Universe II Debug and Initialization Notes
5 Page 7
The Universe II can only be reset through hardware, software can only cause the
Universe II to assert its reset outputs. In order to reset the Universe II through software,
the Universe II reset outputs must be connected to the Universe II reset inputs. For
example, the SW_LRST bit in the MISC_CTL register, which asserts the LRST#
output, which will not reset the Universe II itself unless LRST# is looped back to RST#.
As described in “Reset Implementation Cautions” of the users manual, there are
potential loopback configurations resulting in permanent reset.
Table 6: Software Reset Mechanism
Register
MISC_CTL
VCSR_SET
VCSR_CLR
Name
SW_LRST
Type
W
SW_SYSRST W
RESET
R/W
SYSFAIL
R/W
RESET
R/W
SYSFAIL
R/W
Function
Software PCI Reset
0=No effect, 1=Initiate LRST#
A read always returns 0.
Software VMEbus SYSRESET
0=No effect, 1=Initiate SYSRST*
A read always returns 0.
Board Reset
Reads: 0=LRST# not asserted, 1=LRST# asserted
Writes: 0=no effect, 1=assert LRST#
VMEbus SYSFAIL
Reads: 0=VXSYSFAIL not asserted,
1=VXSYSFAIL asserted
Writes:0=no effect, 1=assert VXSYSFAIL
Board Reset
Reads: 0=LRST# not asserted, 1=LRST# asserted
Writes: 0=no effect, 1=negate LRST#
VMEbus SYSFAIL
Reads: 0=VXSYSFAIL not asserted,
1=VXSYSFAIL asserted
Writes:0=no effect, 1=negate VXSYSFAIL
1.2.5.2
Universe II Reset Circuitry
For Information on the Reset Circuitry and the effects of various reset events of the
Universe II refer to the Universe II User’s Manual. The manual is available on the
Tundra website at www.tundra.com.
8091142_AN005_01
Universe II Debug and Initialization Notes
11 Page |
Páginas | Total 20 Páginas | |
PDF Descargar | [ Datasheet CA91C142.PDF ] |
Número de pieza | Descripción | Fabricantes |
CA91C142 | PCI to VMEbus Bridge | Tundra Semiconductor Corporation |
CA91C142 | Debug and Initialization Notes | Tundra |
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