DataSheet.es    


PDF ICS9112-16 Data sheet ( Hoja de datos )

Número de pieza ICS9112-16
Descripción Low Skew Output Buffer
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



Hay una vista previa y un enlace de descarga de ICS9112-16 (archivo pdf) en la parte inferior de esta página.


Total 8 Páginas

No Preview Available ! ICS9112-16 Hoja de datos, Descripción, Manual

m ICS9112-16Integrated
oCircuit
.cSystems, Inc.
Low SktaeSwheOeut4tpUut BufferGeneral Description
.DaThe ICS9112-16 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology
wto align, in both phase and frequency, the REF input with
wthe CLKOUT signal. It is designed to distribute high speed
clocks in PC systems operating at speeds from 25 to
w133 MHz.
mICS9112-16 is a zero delay buffer that provides
osynchronization between the input and output. The
synchronization is established via CLKOUT feed back to
.cthe input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
UThe ICS9112-16 comes in an eight pin 150 mil SOIC or 173
mil TSSOP package. It has five output clocks. In the
t4absence of REF input, will be in the power down mode. In
this mode, the PLL is turned off and the output buffers are
pulled low. Power down mode provides the lowest power
econsumption for a standby condition.
Features
• Zero input - output delay
• Frequency range 25 - 133 MHz (3.3V)
• High loop filter bandwidth ideal for Spread
Spectrum applications.
• Less than 200 ps Jitter between outputs
• Skew controlled outputs
• Skew less than 250 ps between outputs
• Available in 8 pin 150 mil SOIC
or 173 mil TSSOP package.
• 3.3V ±10% operation
ataSheBlock Diagram
Pin Configuration
www.D m8 pin SOIC,TSSOP
www.DataSheet4U.co0047H—09/01/04

1 page




ICS9112-16 pdf
ICS9112-16
Output to Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded
than CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause
them to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded Equally
REF input and CLK(1-4)
outputs loaded equally, with
CLKOUT loaded More.
REF input and CLK(1_4)
outputs loaded equally, with
CLKOUT loaded Less.
0047H—09/01/04
Timing diagrams with different loading configurations
5

5 Page










PáginasTotal 8 Páginas
PDF Descargar[ Datasheet ICS9112-16.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
ICS9112-16Low Skew Output BufferIntegrated Circuit Systems
Integrated Circuit Systems
ICS9112-17Low Skew Output BufferIntegrated Circuit Systems
Integrated Circuit Systems
ICS9112-18Zero Delay / Low Skew BufferIntegrated Circuit Systems
Integrated Circuit Systems

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar