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PDF M37643F8 Data sheet ( Hoja de datos )
| Número de pieza | M37643F8 | |
| Descripción | Single-Chip 8-Bit CMOS Microconputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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7643 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0054-0100Z
Rev.1.00
Jul 30, 2003
DESCRIPTION
The 7643 group is the 8-bit microcomputer based on the 7600 series
core (740 family core compatible) technology.
The 7643 group is designed for PC peripheral devices, including the
USB, DMAC, Serial I/O, UART, Timer and so on.
FEATURES
<Microcomputer mode)
●Basic machine-language instructions ....................................... 71
●Minimum instruction execution time ..................................... 83 ns
(at 24 MHz oscillation frequency)
●Memory size
ROM ............................................................................. 32 Kbytes
RAM ................................................................................ 1 Kbytes
●Programmable input/output ports ............................................. 66
●Software pull-up resistors .................................................. Built-in
●Interrupts ................................................... 14 sources, 14 vectors
(external 3 including Key input, internal 10, software 1)
●USB function control unit
Transceiver ............................... Full-Speed USB2.0 specification
●Timers .................................................... 8-bit ✕ 3 (Timers 1, 2, 3)
●Serial I/O ......................................................................... 8-bit ✕ 1
●UART .............................................................................. 8-bit ✕ 1
●DMAC .......................................................................... 2 channels
●Clock generating circuit ..................................................... Built-in
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
At 24 MHz oscillation frequency, φ = 12 MHz ......... 4.15 to 5.25 V
At 24 MHz oscillation frequency, φ = 6 MHz ........... 3.00 to 3.60 V
●Operating temperature range .................................... –20 to 70°C
● Packages
FP ............................................................. 80P6N-A (80-pin QFP)
HP ........................................................... 80P6Q-A (80-pin LQFP)
<Flash memory mode>
●Power source voltage
At 24 MHz oscillation frequency, φ = 12 MHz ......... 4.15 to 5.25 V
At 24 MHz oscillation frequency, φ = 6 MHz ........... 3.00 to 3.60 V
●Program/Erase voltage
.................................. VCC = 4.50 V to 5.25 V, or 3.00 V to 3.60 V
.................................................................. VPP = 4.50 V to 5.25 V
At 24 MHz oscillation frequency, φ = 6 MHz (See Table 20.)
●Memory size
Flash ROM .................................................................... 32 Kbytes
RAM ............................................................................. 2.5 Kbytes
●Flash memory mode ....................................................... 3 modes
Parallel I/O mode
Standard serial I/O mode
CPU rewrite mode
●Programming method ....................... Programming in unit of byte
●Erasing method
Batch erasing
Block erasing
●Program/Erase control by software command
●Command number ................................................... 6 commands
●Number of times for programming/erasing ............................. 100
●ROM code protection
Available in parallel I/O mode and standard serial I/O mode
●Operating temperature range (at programming/erasing) ..............
...................................................................... Normal temperature
APPLICATION
Audio, musical instrument, printer, scanner, modem, other PC pe-
ripheral devices
■Notes
1. The specifications of this product are subject to change be-
cause it is under development. Inquire the use of Renesas
Technology Corporation.
2. The flash memory version cannot be used for application em-
bedded in the MCU card.
Rev.1.00 Jul 30, 2003 page 1 of 119
1 page  
7643 Group
Table 2 Pin description (2)
Pin
P60–P67
Name
I/O port P6
Function
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
Function except a port function
P70,
__________
P71/HOLD,
P72,
__________
P73/HLDA,
P74
__________
P80/SRDY,
P81/SCLK,
P82/SRXD,
P83/STXD,
P84/UTXD,
P85/URXD,
________
P86/CTS,
________
P87/RTS
I/O port P7
I/O port P8
• 5-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually pro-
grammed as either input or output.
• Serial I/O pin
• UART pin
Remarks
•DMAOUT pin
If externally detecting the timing of DMA execution, use the signal from this pin. It is “H” level during DMA transferring. This signal is valid in the memory expansion
and microprocessor modes.
•SYNCOUT pin
If externally detecting the timing of OP code fetch, use the signal from this pin. This signal is valid in the memory expansion and microprocessor modes.
Rev.1.00 Jul 30, 2003 page 5 of 119
5 Page 
7643 Group
[CPU Mode Registers A, B (CPUMA, CPUMB)] 000016, 000116
The CPU mode register contains the stack page select bit and the
CPU operating mode select bit and so on.
The CPU mode registers are allocated at address 000016, 000116.
■ Notes
Do not use the microprocessor mode in the flash memory version.
b7 b0
1 CPU mode register A (address 000016)
CPMA
Processor mode bits
b1b0
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Microprocessor mode (Note 1)
1 1: Not available
Stack page select bit
0: Page 0
1: Page 1
Fix to “1”.
Sub-clock (XCIN-XCOUT) control bit
0: Stopped
1: Oscillating
Main clock (XIN-XOUT) control bit
0: Oscillating
1: Stopped
Internal system clock select bit (Note 2)
0: External clock (XIN-XOUT or XCIN-XCOUT)
1: fSYN
External clock select bit
0: XIN-XOUT
1: XCIN-XCOUT
Notes 1: This is not available in the flash memory version.
2: When (CPMA 6, 7) = (0, 0), the internal system clock can be selected between f(XIN) or f(XIN)/2 by CCR7.
The internal clock φ is the internal system clock divided by 2.
b7
10
Fig. 8 Structure of CPU mode register
b0
CPU mode register B (address 000116)
CPMB
Slow memory wait select bits
b1b0
0 0: No wait
0 1: One-time wait
1 0: Two-time wait
1 1: Three-time wait
Slow memory wait mode select bits
b3b2
0 0: Software wait
0 1: Not available
1 0: RDY wait
1 1: Software wait plus RDY input anytime wait
Expanded data memory access bit
0: EDMA output disabled
1: EDMA output enabled
HOLD function enable bit
0: HOLD function disabled
1: HOLD function enabled
Reserved bit (“0” at read/write)
Fix to “1”.
Rev.1.00 Jul 30, 2003 page 11 of 119
11 Page | ||
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