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Número de pieza | ICS9148-111 | |
Descripción | Frequency Generator & Integrated Buffers | |
Fabricantes | Integrated Circuit Systems | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de ICS9148-111 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
No Preview Available ! Integrated
Circuit
Systems, Inc.
ICS9148-111
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
Recommended Application:
ALI (Aladdin V ) mobile.
Output Features:
• 3 - CPUs @ 2.5V/3.3V, up to 100MHz.
• 3 - AGPCLK @ 3.3V
• 13 - SDRAM @ 3.3V, up to 100MHz.
• 6 - PCI @ 3.3V, including one free running.
• 1 - 48MHz, @ 3.3V fixed.
• 1 - REF @ 3.3V, 14.318MHz.
Features:
• Up to 100MHz frequency support
• Support power management: CPU, PCI, AGP stop and,
Power down Mode from I2C programming.
• Spread spectrum for EMI control (0 to -0.6%, ± 0.25%).
• Uses external 14.318MHz crystal
• FS pins for frequency select
Key Specifications:
• CPU – CPU: <250ps
• SDRAM - SDRAM: <250ps
• AGP-AGP: <250ps
• PCI – PCI: <500ps
• CPU-SDRAM <500ps
• CPU(early)-PCI: 1-4ns, Center 2-6ns
• CPU-AGP <500ps
Pin Configuration
48-Pin 300mil SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Block Diagram
Functionality
CPU, PCI AGP
FS2 FS1 FS0 SDRAM (MHz) (MHz)
(MHz)
1 1 1 100 33.33 66.67
1 1 0 95.25 31.75 63.50
1 0 1 83.3 33.30 66.60
100
75 30.00 60.00
0 1 1 91.5 30.50 61.00
0 1 0 96.22 32.07 64.15
0 0 1 66.8 33.40 66.80
000
60 30.00 60.00
REF,
IOAPIC
(MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
9148-111 Rev A 10/19/99
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page ICS9148-111
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 7
Bit 6:4
Bit 3
Bit 2
Bit 1
Bit 0
Description
Must be 0 for normal operation
0 -- +/- 0.25% Spread Spectrum Modulation
1 -- +/- 0.6% Spread Spectrum Modulation
Bit6 Bit5 Bit4
111
110
101
100
CPU Clock
100
95.25
83.3
75
PCI
33.33
31.75
33.30
30.00
011 91.5 30.50
010
96.22
32.07
001 66.8 33.40
000 60 30.00
0 - Frequency is selected by hardware select, Latched inputs
1 - Frequency is selected by Bit 6:4 (above)
Must be 0 for normal operation
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1 - Tristate all outputs
AGP
66.67
63.50
66.60
60.00
61.00
64.15
66.80
60.00
PWD
0
Note 1
0
0
0
0
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 000, and if
bit 3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle.
Note: PWD = Power-Up Default
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
40
-
41
43
44
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
SDRAM12 (Act/Inact)
(Reserved)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
-
13
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
PCICLK_F (Act/Inact)
(Reserved)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Third party brands and names are the property of their respective owners.
5
5 Page ICS9148-111
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-111. It is used to turn off the PCICLK (0:5) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9148-111 internally. The minimum that the PCICLK (0:5) clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full
high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK
clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
Third party brands and names are the property of their respective owners.
11
11 Page |
Páginas | Total 18 Páginas | |
PDF Descargar | [ Datasheet ICS9148-111.PDF ] |
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