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PDF ICS9148-17 Data sheet ( Hoja de datos )
| Número de pieza | ICS9148-17 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9148 - 17
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-17 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel PentiumPro
or Cyrix. Eight different reference frequency multiplying factors
are externally selectable with smooth frequency transitions.
Features include four CPU, six PCI, two AGP (=2xPCI) and
Twelve SDRAM clocks. Two reference outputs are available
equal to the crystal frequency. One 48 MHz for USB, and one
24 MHz clock for Super IO. Built in ±1.5%, 0.6% center or down
spread spectrum modulation to reduce EMI. Serial
programming I2C interface allows changing functions, stop
clock programing and frequency selection. Additionally, the
device meets the Pentium power-up stabilization, which
requires that CPU and PCI clocks be stable within 2ms after
power-up.
Features
3.3V outputs: SDRAM, AGP, PCI, REF, 48/24 MHz
2.5V or 3.3V outputs: CPU
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
CPU to PCI skew = 2 to 6ns
No external load cap for CL=18pF crystals
250 ps max CPU, PCI clock skew
Smooth CPU frequency transition among all CPU
frequencies.
I2C interface for programming
2ms power up clock stable time
Clock duty cycle 45-55%.
48 pin 300 mil SSOP package
3.3V operation, 5V tolerant inputs.
Pin Configuration
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50±5% duty cycle. The REF and 24 and 48
MHz clock outputs typically provide better than 0.5V/ns slew
rates.
Block Diagram
X1
X2
FS(0:2)
MODE
CPU3.3#_2.5
3
CPU_STOP#
PCI_STOP#
SDATA
SCLK
PLL2
XTAL
OSC
PLL1
Spread
Spectrum
LATCH
POR
5
Control
Logic
Config.
Reg.
/2
STOP
STOP
CPU_STOP
PCI
CLOCK
DIVDER
STOP
PCI_STOP
9148-17 Rev G 4/27/00
48MHz
24MHz
REF (0:1)
2 AGP(0:1)
4 CPUCLK (0:3)
12 SDRAM (0:11)
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
5 PCICLK (0:4)
PCICLK_F
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
VDD4 = AGP (0:1)
VDDL = CPUCLK (0:3)
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
1 page  
ICS9148 - 17
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 7
Description
0 - ±1.5% Spread Spectrum Modulation
1 - ±0.6% Spread Spectrum Modulation
Bit 6,5,4 CPU Clock
PCI
AGP
PWD
0
Bit
6:4
Bit 3
Bit 2
Bit 1
Bit 0
111 100.2
33.4 66.8
110 90
30 60
101 83.3
32 64
100 75
32 64
011 75
37.5 75
010
68.5
34.25
68.5
001 66.8
33.4 66.8
000 60
30 60
0 - Frequency is selected by hardware select,
Latched Inputs
1 - Frequency is selected by Bit 6:4 (above)
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Note 1
0,0,0
0
0
0
0
Note 1. Default at Power-up will be for latched logic inputs
to define frequency. Bits 4, 5, 6 are default to 000,
and if bit 3 is written to a 1 to use bits 6:4, then
these should be defined to desired frequency at same
write cycle.
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation
5
5 Page 
ICS9148 - 17
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP
Output High Voltage VOH2A IOH = -28 mA
Output Low Voltage VOL2A IOL = 27 mA
Output High Current IOH2A VOH = 2.0 V
Output Low Current
IOL2A VOL = 0.8 V
Rise Time
tr2A1 VOL = 0.4 V, VOH = 2.4 V
Fall Time
tf2A1 VOH = 2.4 V, VOL = 0.4 V
Duty Cycle
dt2A1 VT = 1.5 V
Skew
tsk2A1 VT = 1.5 V
Jitter, One Sigma
Jitter, Absolute
tj1s2A1
tjabs2A1
VT = 1.5 V
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
2.5
33
45
-250
2.6
0.35
-29
37
1.75
1.1
50
50
65
165
MAX
0.4
-23
2
2
55
250
150
250
UNITS
V
V
mA
mA
ns
ns
%
ps
ps
ps
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX
Output High Voltage VOH2B IOH = -8 mA
2 2.2
Output Low Voltage VOL2B IOL = 12 mA
0.3
Output High Current IOH2B VOH = 1.7 V
-20
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
IOL2B
tr2B1
tf2B1
dt2B1
tsk2B1
VOL = 0.7 V
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
VT = 1.25 V
19
40
26
1.5
1.6
47
60
Jitter, Single Edge
Displacement2
Jitter, One Sigma
Jitter, Absolute
tjsed2B1
tj1s2B1
tjabs2B1
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
200
65
-300 160
1 Guaranteed by design, not 100% tested in production.
2 Edge displacement of a period relative to a 10-clock-cycle rolling average period.
0.4
-16
1.8
1.8
55
250
250
150
300
UNITS
V
V
mA
mA
ns
ns
%
ps
ps
ps
ps
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ICS9148-17.PDF ] | |
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