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PDF ICS9148-37 Data sheet ( Hoja de datos )
| Número de pieza | ICS9148-37 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9148 - 37
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-37 is the single chip clock solution for
Desktop/Notebook designs using the VIA MVP3 style
chipset. It provides all necessary clock signals for such a
system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB.This simplifies EMI qualification without resorting to
board design iterations or costly shielding.The ICS9148-
37 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection. The
SD_SEL latched input allows the SDRAM frequency to
follow the CPUCLK frequency(SD_SEL=1) or the AGP
clock frequency(SD_SEL=0)
Block Diagram
Features
• Generates the following system clocks:
- 4 CPU(2.5V/3.3V) upto 100MHz.
- 6 PCI(3.3V) @ 33.3MHz
- 2AGP(3.3V) @ 2 x PCI
- 12 SDRAMs(3.3V) @ either CPU or AGP
- 2 REF (3.3V) @ 14.318MHz
• Skew characteristics:
- CPU – CPU<250ps
- SDRAM – SDRAM < 250ps
- CPU – SDRAM < 250ps
- CPU–AGP: < 1ns
- CPU(early) – PCI : 1-4ns
• Supports Spread Spectrum modulation +0.25, ±0.6%
• Serial I2C interface for Power Management,
Frequency Select, Spread Spectrum.
• Efficient Power management scheme through PCI and
CPU STOP CLOCKS.
• Uses external 14.318MHz crystal
• 48 pin 300mil SSOP.
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
VDD4 = AGP (0:1)
VDDL = CPUCLK (0:3)
0143G—08/04/04
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
1 page  
ICS9148 - 37
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register
(default = 0)
Bit Description
Bit 7
0 - ±0.25% Spread Spectrum Modulation
1 - ±0.6% Spread Spectrum Modulation
Bit6 Bit5 CPU Clock PCI AGP
Bit4
111 100 33.3 66.6
110 95.25 31.75 63.5
Bit 101
83.3 33.3 66.6
6:4 100
75 30 60
011 75 37.5 75
010 68.5 34.25 68.5
001 66.8 33.4 66.8
000 60 30 60
0 - Frequency is selected by hardware
Bit 3
select,
Latched Inputs
1 - Frequency is selected by Bit 6:4 (above)
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
Bit 1
0 - Normal
1 - Spread Spectrum Enabled
Bit 0
0 - Running
1- Tristate all outputs
PWD
0
Note
1
0
0
0
0
Byte 1: CPU, Active/Inactive
Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
40
41
43
44
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 2: PCI Active/Inactive
Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
15
13
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
PCICLK_F (Act/Inact)
AGP0 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
0143G—08/04/04
5
5 Page 
ICS9148 - 37
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP
2
VSS - 0.3
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors -5
VIN = 0 V; Inputs with pull-up resistors
-200
CL = 0 pF; 66.8 MHz
0.1
2.0
-100
100
Input frequency
Input Capacitance1
Fi VDD = 3.3 V;
CIN Logic Inputs
Transition Time1
Settling Time1
Clk Stabilization1
CINX
Ttrans
Ts
TSTAB
X1 & X2 pins
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
Skew1
TCPU-SDRAM1 VT = 1.5 V; SDRAM Leads
TCPU-PCI1 VT = 1.5 V; CPU Leads
TCPU-AGP VT = 1.5 V; CPU Leads
1Guaranteed by design, not 100% tested in production.
14.318
27 36
-500 200
1 2.8
-1 0
MAX
VDD + 0.3
0.8
5
160
5
45
2
2
500
4
1
UNITS
V
V
mA
mA
mA
mA
MHz
pF
pF
ms
ms
ms
ps
ns
ns
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX
Operating
Supply Current
IDD2.5OP
CL = 0 pF; 66.8 MHz
10 20
Skew1
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Lead -500
TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
1
200
2.7
500
4
1Guaranteed by design, not 100% tested in production.
UNITS
mA
ps
ns
0143G—08/04/04
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS9148-37.PDF ] | |
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