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PDF ICS9148-75 Data sheet ( Hoja de datos )
| Número de pieza | ICS9148-75 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9148 - 75
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Mother Boards
General Description
The ICS9148-75 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro™, AMD™ or Cyrix™. Sixteen different reference
frequency multiplying factors are externally selectable with
smooth frequency transitions.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-75
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection. The
SDRAM12 output may be used as a feed back into an off chip
PLL.
Block Diagram
Features
• Generates the following system clocks:
- 3 CPU(2.5V/3.3V) up to 100MHz.
- 6 PCI(3.3V) @ 33.3MHz (including one free
running PCICLK)
- 3AGP(3.3V) @ 2 x PCI
- 13 SDRAMs(3.3V) up to 100MHz
- 1 REF (3.3V) @ 14.318MHz
- 1 - 48MHz (3.3V) fixed
• Skew characteristics:
- CPU – CPU<250ps
- CPU(early) – PCI : 1-4ns
- AGP – PCI: 250ps
- PCI – PCI <500ps
• Supports Spread Spectrum modulation & I2C
programming for Power Management, Frequency Select
• Efficient Power management scheme through power
down PCI, AGP and CPU_STOP clocks.
• Uses external 14.318MHz crystal
• 48 pin 300mil SSOP.
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core
VDD4 =AGP(1:2)
VDD5 = Fixed PLL, 48MHz ,AGP0
VDDL= CPUCLK(0:3)
9148-75 Rev C 3/01/00
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
1 page  
ICS9148 - 75
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
Dummy Command Code
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Stop Bit
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
ICS (Slave/Receiver)
ACK
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
5
5 Page 
ICS9148 - 75
Preliminary Product Preview
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS9148-75
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
Programming
Header
Via to Gnd
Via to
VDD
2K W
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
11
11 Page | ||
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