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PDF ICS9148-82 Data sheet ( Hoja de datos )

Número de pieza ICS9148-82
Descripción Frequency Generator & Integrated Buffers
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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Integrated
Circuit
Systems, Inc.
ICS9148 - 82
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-82 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel PentiumPro
or Cyrix. Eight different reference frequency multiplying factors
are externally selectable with smooth frequency transitions.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-82
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection. The
SDRAM12 output may be used as a feed back into an off chip
PLL.
Features
• Generates the following system clocks:
- 3 CPU(2.5V/3.3V) upto 100MHz.
- 6 PCI(3.3V) @ 33.3MHz
- 3AGP(3.3V) @ 2 x PCI
- 13 SDRAMs(3.3V) up to 100MHz
- 1 REF (3.3V) @ 14.318MHz
• Skew characteristics:
- CPU – CPU<250ps
- CPU(early) – PCI : 1-4ns, Center 2.6ns
- AGP - PCI: 500ps
• Supports Spread Spectrum modulation & I2C
programming for Power Management, Frequency Select
• Efficient Power management scheme through PCI and
CPU STOP CLOCKS.
• Uses external 14.318MHz crystal
• 48 pin 300mil SSOP.
Block Diagram
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:12), supply for PLL core
VDD4 =AGP(1:2)
VDD5 = Fixed PLL, 48MHz ,AGP0
VDDL= CPUCLK(0:2)
9148-82 Rev A 3/25/99
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

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ICS9148-82 pdf
ICS9148 - 82
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit Description
Must be 0 for normal operation
Bit 7 0 - ±0.25% Spread Spectrum Modulation
1 - ±0.6% Spread Spectrum Modulation
Bit6 Bit5 Bit4 CPU Clock
111 100
110 95.25
Bit
6:4
101
100
011
83.3
75
75
010 68.5
001 66.8
000 90
PCI
33.3
31.75
33.3
30
37.5
34.25
33.4
30
AGP
66.6
63.5
66.6
60
75
68.5
66.8
60
0 - Frequency is selected by hardware select,
Bit 3 Latched Inputs
1 - Frequency is selected by Bit 6:4 (above)
Must be 0 for normal operation
Bit 2 0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
Bit 1
0 - Normal
1 - Spread Spectrum Enabled
Bit 0
0 - Running
1- Tristate all outputs
PWD
0
Note1
0
0
0
0
Note 1. Default at Power-up will be for latched logic inputs
to define frequency. Bits 4, 5, 6 are default to 000,
and if bit 3 is written to a 1 to use Bits 6:4, then
these should be defined to desired frequency at same
write cycle.
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
40
-
41
43
44
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
SDRAM12 (Act/Inact)
(Reserved)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 2: PCIActive/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
-
13
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
PCICLK_F (Act/Inact)
(Reserved)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
5

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ICS9148-82 arduino
ICS9148 - 82
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD, VDDL = 3.3 V +/-5% (unles s otherwis e s tated)
PAR AM ETER
SYM B OL
C ONDIT IONS
M IN TYP M AX UNITS
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Current
IIH VIN = VDD
Input Low Current
IIL1 VIN = 0 V; Inputs with no pull-up resistors
Input Low Current
IIL2 VIN = 0 V; Inputs with pull-up resistors
Op e ra t i n g
IDD3.3OP66 CL = 0 pF; Select @ 66.8M Hz
Supply Current
IDD3.3OP100 CL = 0 pF; Select @ 100M Hz
Input frequency
Fi VDD = 3.3 V;
Input Capacitance1
CIN Logic Inputs
C INX
X1 & X2 pins
Transition Time1
TTrans To first crossing of target Freq.
Settling Time1
TS From first crossing to 1% of target Freq.
Clk Stabilization1
TSTAB From VDD = 3.3 V to 1% target Freq.
TCPU-PCI1 VT=1.5 V; VTL=1.25 V; f=66/100 MHz
Skew1
TCPU-PCI1 VT=1.5 V;VTL=1.25 V; f=83/75 M Hz
TAGP-PCI1 VT = 1.5 V; AGP leads
1Guaranteed by design, not 100% tested in production.
2
VSS-0 .3
-5
-2 0 0
12
27
1
1
VDD+0 .3
0 .8
0.1 5
2 .0
-1 0 0
112
160
141
14.318 16
5
36 45
0.65 2
0.36 3
<2 2
2.45 4
3.8 4
390 500
V
V
µA
µA
µA
mA
M Hz
pF
pF
ms
ms
ms
ns
ns
ps
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unles s otherwis e s tated)
PA RA M ETER
SYM BOL
CONDITIONS
MIN TYP M A X UNITS
Op e ra t in g
Supply Current
ID D 2.5O P 66
ID D 2.5O P 100
CL = 0 pF; Select @ 66.8 M Hz
CL = 0 pF; Select @ 100 M Hz
14 20
mA
18 20
Skew1
T C PU-PC I1
T C PU-PC I1
VT=1.5 V; VTL=1.25 V; f=66/100 M Hz
VT=1.5 V;VTL=1.25 V; f=83/75 M Hz
TAGP-PCI1 VT=1.5 V; AGP Leads
1Guaranteed by des ign, not 100% tes ted in production.
1 2.45
4
ns
1 3.8 4
ns
220 500
ns
11

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