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PDF ICS9148-93 Data sheet ( Hoja de datos )
| Número de pieza | ICS9148-93 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9148 - 93
Advance Information
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-93 is the single chip clock solution for Desktop/
Notebook designs using the VIA MVP3 style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-93
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection. The SD_SEL
latched input allows the SDRAM frequency to follow the
CPUCLK frequency(SD_SEL=1) or the AGP clock
frequency(SD_SEL=0).
Block Diagram
Features
Generates the following system clocks:
- 4 CPU(2.5V/3.3V) upto 100MHz.
- 6 PCI(3.3V) @ 33.3MHz
- 2AGP(3.3V) @ 2 x PCI
- 12 SDRAMs(3.3V) @ either CPU orAGP
- 2 REF (3.3V) @ 14.318MHz
Skew characteristics:
- CPU CPU<250ps
- SDRAM SDRAM < 250ps
- CPU SDRAM < 250ps
- CPU(early) PCI : 1-4ns
Supports Spread Spectrum modulation +0.25, ±0.6%
Serial I2C interface for Power Management, Frequency
Select, Spread Spectrum.
Efficient Power management scheme through PCI and CPU
STOP CLOCKS.
Uses external 14.318MHz crystal
48 pin 300mil SSOP.
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
VDD4 = AGP (0:1)
VDDL = CPUCLK (0:3)
9148-93 Rev - 1/22/99
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
1 page  
ICS9148 - 93
Advance Information
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
40
41
43
44
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 2: PCIActive/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
15
13
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
PCICLK_F (Act/Inact)
AGP0 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
28
29
31
32
34
35
37
38
PWD
1
1
1
1
1
1
1
1
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
47
-
-
46
2
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
AGP1(Act/Inact)
(Reserved)
(Reserved)
REF1 (Act/Inact)
REF0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
17
18
20
21
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM11 (Act/Inact)
(Desktop Mode Only)
SDRAM10 (Act/Inact)
(Desktop Mode Only)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
5
5 Page 
ICS9148 - 93
Advance Information
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX
Output High Voltage VOH2B IOH = -8 mA
2 2.2
Output Low Voltage VOL2B IOL = 12 mA
0.3
Output High Current IOH2B VOH = 1.7 V
-20
Output Low Current IOL2B VOL = 0.7 V
19 26
Rise Time
tr2B1 VOL = 0.4 V, VOH = 2.0 V
1.5
Fall Time
tf2B1 VOH = 2.0 V, VOL = 0.4 V
1.6
Duty Cycle
dt2B1 VT = 1.25 V
40 47
Skew
tsk2B1 VT = 1.25 V
60
Jitter, Single Edge
Displacement2
tjsed2B1 VT = 1.25 V
200
Jitter, One Sigma tj1s2B1 VT = 1.25 V
65
Jitter, Absolute tjabs2B1 VT = 1.25 V
-300 160
1 Guaranteed by design, not 100% tested in production.
2 Edge displacement of a period relative to a 10-clock-cycle rolling average period.
0.4
-16
1.8
1.8
55
250
250
150
300
UNITS
V
V
mA
mA
ns
ns
%
ps
ps
ps
ps
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN
TYP
Output High Voltage VOH2A IOH = -28 mA
Output Low Voltage VOL2A IOL = 27 mA
Output High Current IOH2A VOH = 2.0 V
Output Low Current
IOL2A VOL = 0.8 V
Rise Time
tr2A1 VOL = 0.4 V, VOH = 2.4 V
Fall Time
tf2A1 VOH = 2.4 V, VOL = 0.4 V
Duty Cycle
dt2A1 VT = 1.5 V
Skew
tsk
1
2A
VT = 1.5 V
Jitter, One Sigma
Jitter, Absolute
tj1s2A1
tjab
s
1
2A
VT = 1.5 V
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
2.5
33
45
-250
2.6
0.35
-29
37
1.75
1.1
50
50
65
165
MAX
0.4
-23
2
2
55
250
150
250
UNITS
V
V
mA
mA
ns
ns
%
ps
ps
ps
11
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| PDF Descargar | [ Datasheet ICS9148-93.PDF ] | |
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