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PDF ICS9147-03 Data sheet ( Hoja de datos )
| Número de pieza | ICS9147-03 | |
| Descripción | Frequency Generator & Integrated Buffers | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9147- 03
Frequency Generator & Integrated Buffers for 686 Series CPUs
General Description
The ICS9147-03 generates all clocks required for high
speed RISC or CISC microprocessor systems such as Intel
PentiumPro, AMD or Cyrix processors. Four bidirectional I/O
pins (FS0, FS1, FS2, BSEL) are latched at power-on to the
functionality table. The Six BUS clocks can be selected as
either synchronous at 1/2 CPU speed or asynchronous at
32MHz selected by BSEL latched input.The inputs provide
for tristate and test mode conditions to aid in system level
testing.These multiplying factors can be customized for
specific applications. Glitch-free stop clock controls
provided for SDRAM(5:8) and SDRAM (9:12) banks
(STP2#, STP3#).
High drive BUS and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30 pF loads. CPU outputs
typically provide better than 1V/ns slew rate into 20pF
loads while maintaining 50±5% duty cycle. The REF clock
outputs typically provide better than 0.5V/ns slew rates.
Seperate buffer supply pin VDDL allows for nominal 3.3V
voltage or reduced voltage swing (from 2.9 to 2.5V) for
CPUL (1:2) and IOAPIC outputs.
Features
• Total of 15 CPU speed clocks:
- Two copies of CPU clock with VDDL (2.5 to 3.3V)
- Twelve (12) SDRAM (3.3v) plus one
CPUH/AGP (3.3V) clocks
• Six copies of BUS clocks (synchronous with CPU clock/2
or asynchronous 32 MHz)
• 250ps output skew window for CPU andSDRAM clocks
and 500ps window BUS clocks. CPU clocks to BUS clocks
skew 1-4ns (CPU early)
• Two copies of Ref. clock @14.31818 MHz (One driven by
VDDL as IOAPIC)
• One 48 MHz (3.3 V TTL) for USB support and single 24
MHz.
• Separate VDDL for CPUL (1:2) clock buffers and IOAPIC to
allow 2.5V output (or Std. Vdd)
• 3.0V – 3.7V supply range w/2.5V compatible outputs
• 48-pin SSOP package
Block Diagram
Pin Configuration
9147-03 Rev A 04/25/01
48-Pin SSOP
Pentium is a trademark of Intel Corporation
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
1 page  
ICS9147- 03
Shared Pin Operation -
Input/Output Pins
Pins 2, 15, 46 and 47 on the ICS9147-03 serve as dual
signal functions to the device. During initial power-up,
they act as input pins. The logic level (voltage) that is
present on these pins at this time is read and stored into a
4-bit internal data latch. At the end of Power-On reset, (see
AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered
clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the device’s
internal logic. Figs. 2a and b provide a single resistor
loading option where either solder spot tabs or a physical
jumper header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
Test Mode Operation
The ICS9147-03 includes a production test verification
mode of operation. This requires that the FS2 and FS1 pins
be programmed to a logic high and the FS0 pin be
programmed to a logic low(see Shared Pin Operation
section). In this mode the device will output the following
frequencies.
Pin
REF, IOAPIC
48MHz
24MHz
CPU, SDRAM
BUS BSEL=1
BUS BSEL=0
Frequency
REF
REF/2
REF/4
REF2
REF/4
REF/3
Note: REF is the frequency of either the crystal connected
between the devices X1and X2, or, in the case of a device
being driven by an external reference clock, the frequency
of the reference (or test) clock on the device’s X1 pin.
Fig. 1
5
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet ICS9147-03.PDF ] | |
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