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PDF ICS9148-02 Data sheet ( Hoja de datos )
| Número de pieza | ICS9148-02 | |
| Descripción | Pentium/ProTM System Clock Chip | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9148-02
Pentium/ProTM System Clock Chip
General Description
The ICS9148-02 is a Clock Synthesizer chip for Pentium and
PentiumPro CPU based Desktop/Notebook systems that will
provide all necessary clock timing.
Features include four CPU, seven PCI and eight SDRAM
clocks. Two reference outputs are available equal to the
crystal frequency. Additionally, the device meets the Pentium
power-up stabilization, which requires that CPU and PCI
clocks be stable within 2ms after power-up.
PWR_DWN# pin allows low power mode by stopping crystal
OSC and PLL stages. For optional power management,
CPU_STOP# can stop CPU (0:3) clocks and PCI_STOP#
will stop PCICLK (0:5) clocks. CPU and IOAPIC output
buffer strength controlled by CPU 3.3_2.5# pin to match
VDDL voltage.
High drive CPUCLK outputs typically provide greater than 1
V/ns slew rate into 20pF loads. PCICLK outputs typically
provide better than 1V/ns slew rate into 30pF loads while
maintaining 50±5% duty cycle. The REF clock outputs typically
provide better than 0.5V/ns slew rates.
The ICS9148-02 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Features
Generates system clocks for CPU, IOAPIC, SDRAM,
PCI, plus 14.314 MHz REF(0:1), USB, Plus Super I/O
Supports single or dual processor systems
I2C serial configuration interface provides output clock
disabling and other functions
MODE input pin selects optional power management
input control pins
Two fixed outputs separately selectable as
24 or 48MHz
Separate 2.5V and 3.3V supply pins
2.5V or 3.3V outputs: CPU, IOAPIC
3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
CPU 3.3_2.5# logic pin to adjust output strength
No power supply sequence requirements
Uses external 14.318MHz crystal
48 pin 300 mil SSOP
Output enable register
for serial port control:
1 = enable
0 = disable
Pin Configuration
Block Diagram
Pentium is a trademark on Intel Corporation.
9148-02 Rev C 1/26/99
48-Pin SSOP
Functionality
VDD (1:4) 3.3V±10%, VDDL1, 2 2.5±5% or 3.3±10% 0-70°C
Crystal (X1, X2) = 14.31818 MHz
SEL
CPUCLK, SDRAM PCICLK
(MHz)
(MHz)
0 60
30
1 66.6 33.3
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
1 page  
Technical Pin Function Descriptions
CPU 3.3_2.5#
This Input pin controls the CPU and IOAPIC output buffer
strength for skew matching CPU and SDRAM outputs to
compensate for the external VDDL supply condition. It is
important to use this function when selecting power supply
requirements for VDDL1,2. A logic 0 (ground) will indicate
2.5V operation and a logic 1 will indicate 3.3V operation.
This pin has an internal pullup resistor to VDD.
PWR_DWN#
This is an asynchronous active Low Input pin used to Power
Down the device into a Low Power state by not removing the
power supply. The internal Clocks are disabled and the VCO
and Crystal are stopped. Powered Down will also place all
the Outputs in a low state at the end of their current cycle.
The latency of Power Down will not be greater than 3ms. The
I2C inputs will be Tri-Stated and the device will retain all
programming information. This input pin only valid when
MODE=0 (Power Management Mode)
CPU_STOP#
This is a synchronous active Low Input pin used to stop the
CPUCLK clocks in an active low state. All other Clocks
including SDRAM clocks will continue to run while this
function is enabled. The CPUCLKs will have a turn ON
latency of at least 3 CPU clocks. This input pin only valid
when MODE=0 (Power Management Mode)
PCI_STOP#
This is a synchronous active Low Input pin used to stop the
PCICLK clocks in an active low state. It will not effect
PCICLK_F nor any other outputs. This input pin only valid
when MODE=0 (Power Management Mode)
I2C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in the
I2C protocol. It will allow read-back of the registers. See
configuration map for register functions. The I2C
specification in Philips I2C Peripherals Data Handbook
(1996) should be followed.
ICS9148-02
5
5 Page 
ICS9148-02
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Voltage
VIH
2 VDD+0.3 V
Input Low Voltage
VIL
VSS-0.3
0.8 V
Input High Current
IIH VIN = VDD
0.1 5 µA
Input Low Current
Input Low Current
IIL1 VIN = 0 V; Inputs with no pull-up resistors
-5 2.0
IIL2 VIN = 0 V; Inputs with pull-up resistors
-200 -100
µA
µA
Operating
IDD3.3OP CL = 0 pF; Select @ 66M
60 100 mA
Supply Current
Power Down
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
400 600 µA
Supply Current
Input frequency
Input Capacitance1
Fi VDD = 3.3 V;
CIN Logic Inputs
14.318
5
MHz
pF
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
CINX X1 & X2 pins
Ttrans To 1st crossing of target Freq.
Ts From 1st crossing to 1% target Freq.
TSTAB From VDD = 3.3 V to 1% target Freq.
TCPU-SDRAM1 VT = 1.5 V
27 36 45 ps
3 ms
ms
3 ms
200 500 ps
TCPU-PCI1 VT = 1.5 V;
1.5 3.2 4.5 ns
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Operating
IDD2.5OP CL = 0 pF; Select @ 66M
5 20 mA
Supply Current
Power Down
IDD2.5PD CL = 0 pF;
0.21 1.0 µA
Supply Current
Skew1
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads
150 500 ps
TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
1 2.8 4 ns
1Guaranteed by design, not 100% tested in production.
11
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