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PDF D17717GC Data sheet ( Hoja de datos )

Número de pieza D17717GC
Descripción UPD17717GC
Fabricantes NEC 
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No Preview Available ! D17717GC Hoja de datos, Descripción, Manual

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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD17717, 17718, 17719
4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED
HARDWARE FOR DIGITAL TUNING SYSTEM
The µPD17717, 17718, and 17719 are 4-bit single-chip CMOS microcontrollers containing hardware for
digital tuning systems.
Provided with a wealth of hardware, these microcontrollers are available in many variations of ROM and RAM
capacities to support various applications.
Therefore, a high-performance, multi-function digital tuning system can be configured with only one chip.
In addition, a one-time PROM model, µPD17P719, which can be written only once and therefore is ideal for
program evaluation and small-scale production of a µPD17717, 17718, or 17719 system, is also available.
FEATURES
• Program memory (ROM)
µPD17717
: 24K bytes (12288 × 16 bits)
µPD17718, 17719: 32K bytes (16384 × 16 bits)
• General-purpose data memory (RAM)
µPD17717, 17718: 1120 × 4 bits
µPD17719
: 1776 × 4 bits
• Instruction execution time
1.78 µs (with fX = 4.5-MHz crystal oscillator)
• PLL frequency synthesizer
Dual modulus prescaler (130 MHz MAX.),
programmable divider, phase comparator, charge
pump
• Abundant peripheral hardware units
General-purpose I/O ports, serial interfaces, A/D
converter, D/A converter (PWM output), BEEP
output, frequency counter
• Many interrupts
External: 6 sources
Internal : 6 sources
• Power-ON reset, CE reset, and power failure
detection circuit
• Supply voltage: VDD = 5 V ± 10 %
ORDERING INFORMATION
Part Number
µPD17717GC-×××-3B9
µPD17718GC-×××-3B9
µPD17719GC-×××-3B9
Package
80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch)
80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch)
80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch)
Remark ××× indicates a ROM code suffix.
Unless otherwise specified, the µPD17719 is treated as the representative model in this document.
The information in this document is subject to change without notice.
Document No. U12330EJ1V0DS00 (1st edition)
Date Published May 1997 N
Printed in Japan
©
1997

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D17717GC pdf
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PIN NAME
AD0-AD5
: A/D converter input
AMIFC
: AM frequency counter input
BEEP0, BEEP1 : BEEP output
CE : Chip enable
EO0, EO1
: Error-out output
FCG0, FGC1 : Frequency counter gate input
FMIFC
: FM frequency counter input
GND0-GND2 : Ground 0 to 2
INT0-INT4
: External interrupt input
PWM0-PWM2 : D/A converter output
P0A0-P0A3 : Port 0A
P0B0-P0B3 : Port 0B
P0C0-P0C3 : Port 0C
P0D0-P0D3 : Port 0D
P1A0-P1A3 : Port 1A
P1B0-P1B3 : Port 1B
P1C0-P1C3 : Port 1C
P1D0-P1D3 : Port 1D
P2A0-P2A2 : Port 2A
P2B0-P2B3 : Port 2B
P2C0-P2C3 : Port 2C
P2D0-P2D2 : Port 2D
µPD17717, 17718, 17719
P3A0-P3A3
P3B0-P3B3
P3C0-P3C3
P3D0-P3D3
REG
RESET
RxD
SB0, SB1
SCK
SCK2, SCK3
SCL
SDA
SI2, SI3
SO2, SO3
TEST
TM0G
TxD
VCOH
VCOL
VDD0, VDD1
XIN, XOUT
: Port 3A
: Port 3B
: Port 3C
: Port 3D
: CPU regulator
: Reset input
: UART serial data input
: SBI serial data I/O
: SBI serial clock I/O
: 3-wire serial clock I/O
: 2-wire serial clock I/O
: 2-wire serial data I/O
: 3-wire serial data input
: 3-wire serial data output
: Test input
: Timer 0 gate input
: UART serial data output
: Local oscillation high input
: Local oscillation low input
: Power supply
: Main clock oscillation
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D17717GC arduino
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µPD17717, 17718, 17719
1. PIN FUNCTIONS
1.1 Pin Function List
Pin No. Symbol
1 INT2
41 INT1
42 INT0
2 P1A3/INT4
3 P1A2/INT3
4 P1A1
5 P1A0/TM0G
6 P3A3
||
9 P3A0
10 P3B3
||
13 P3B0
14 P2A2
15 P2A1/FCG1
16 P2A0/FCG0
Function
Edge-detectable vectored interrupt input pins. Rising or falling edge can be
specified.
Output Form
Port 1A multiplexed with external interrupt request signal input and event
signal input pins.
• P1A3 through P1A0
• 4-bit input port
• INT4, INT3
• Edge-detectable vectored interrupt
• TM0G
• Input for gate of 8-bit timer 0
At reset
With clock stopped
Power-ON reset WDT&SP reset
CE reset
Input
Input
Retained
(P1A3 through P1A0) (P1A3 through P1A0)
Retained
4-bit I/O port.
Can be set in input or output mode in 4-bit units.
CMOS
push-pull
At reset
With clock stopped
Power-ON reset WDT&SP reset
CE reset
Input
Input
Retained
Retained
4-bit I/O port.
Can be set in input or output mode in 4-bit units.
CMOS
push-pull
At reset
With clock stopped
Power-ON reset WDT&SP reset
CE reset
Input
Input
Retained
Retained
Port 2A multiplexed with external gate counter input pins.
• P2A2 through P2A0
• 3-bit I/O port
• Can be set in input or output mode in 1-bit units.
• FCG1, FCG0
• Input for external gate counter
CMOS
push-pull
At reset
With clock stopped
Power-ON reset WDT&SP reset
CE reset
Input
Input
Retained
Retained
(P2A2 through P2A0) (P2A2 through P2A0) (P2A2 through P2A0) (P2A2 through P2A0)
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