DataSheet.es T-51863D150J-FW-A-AE Hoja de datos PDF


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Número de pieza T-51863D150J-FW-A-AE
Descripción LCD_Module
Fabricantes OPTREX 
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T-51863D150J-FW-A-AE datasheet

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T-51863D150J-FW-A-AE pdf
VCC-dip conditions:
1) When 2.6 V VCC < 3.0 V, td 10 ms
2) When VCC < 2.6 V
VCC-dip conditions should also follow the power and signals sequence.
VCC
td
*2) Typical current condition:
64-gray-bar-pattern(6 bit)
256-gray-bar-pattern(8 bit)
768 line mode
VCC = +3.3 V, fH = 48.4 kHz, fV = 60 Hz, fCLK = 65 MHz
(2) Backlight
ITEM
SYMBOL MIN.
TYP. MAX. UNIT
Ta = 25°C
Remarks
Lamp Voltage
VL
--
620
-- Vrms
IL = 6.5 mArms
Lamp Current
IL 3.5 6.5 8.0 mArms
*1),*5)
Lamp Frequency
FL 40 -- 70 kHz
*2)
1300
--
-- Vrms
Ta = 25°C
Starting Lamp Voltage
VS 1500 --
-- Vrms
Ta = 0°C
1650
--
-- Vrms
Ta = 20°C
Lamp Life Time
LT 50000 --
--
h
*3),*4) IL = 6.5 mArms,
Continuous Operation
*1) Lamp Current measurement method (The current meter is inserted in low voltage line.)
CTL
A
CTL
CTH
A
LCD
Module
CTH
CTL
A
Inverter
Power
Supply
CTL
CTH
A
CTH
*2) Lamp frequency of inverter may produce interference with horizontal synchronous frequency,
and this may cause horizontal beat on the display. Therefore, please adjust lamp frequency, and
keep inverter as far from module as possible or use electronic shielding between inverter and
module to avoid the interference.
*3) Lamp life time is defined as the time either when the brightness becomes 50% of the initial
value, or when the starting lamp voltage does not meet the value specified in this table.
T-51863D150J-FW-A-AE (AE) No. 2004-0161
OPTREX CORPORATION
Page 5/37

5 Page

T-51863D150J-FW-A-AE arduino
6. INTERFACE TIMING
LVDS transmitter input signal
(1) Timing Specifications
ITEM
Frequency
DCLK
Period
Horizontal Active Time
Horizontal Front Porch
Horizontal Back Porch
DENA Vertical Active Time
Vertical Front Porch
Vertical Back Porch
Frequency
HD Period
Low Width
Frequency
VD Period
Low Width
SYMBOL
fCLK
tCLK
tHA
tHFP
tHBP
tVA
tVFP
tVBP
fH
tH
tWHL
fV
tV
tWVL
MIN.
50
12.5
1024
0
4
768
2
1
42.4
16.6
1
55
13.3
5
TYP.
65
15.4
1024
24
296
768
3
35
48.4
20.7
136
60
16.7
6
MAX.
80
20
1024
--
--
768
--
--
60
23.6
--
75
18.2
--
UNIT
MHz
ns
tCLK
tCLK
tCLK
tH
tH
tH
kHz
µs
tCLK
Hz
ms
tH
[Note]
1) Polarities of HD and VD are negative in this specification.
2) DENA (Data Enable) should always be positive polarity as shown in the timing specification.
3) DCLK should appear during all invalid period, and HD should appear during invalid period of
frame cycle.
4) LVDS timing follows the timing specifications of LVDS receiver IC: THC63LVDF84A(Thine).
5) tVA + tVFP + tVBP 1024
6) tHFP + tHBP < 512
T-51863D150J-FW-A-AE (AE) No. 2004-0161
OPTREX CORPORATION
Page 10/37

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