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PDF ICX039DNB Data sheet ( Hoja de datos )

Número de pieza ICX039DNB
Descripción Diagonal 8mm (Type 1/2) CCD Image Sensor for PAL Color Video Cameras
Fabricantes Sony Corporation 
Logotipo Sony Corporation Logotipo



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ICX039DNB
Diagonal 8mm (Type 1/2) CCD Image Sensor for PAL Color Video Cameras
Description
The ICX039DNB is an interline CCD solid-state
image sensor suitable for PAL color video cameras
with a diagonal 8mm (Type 1/2) system. Smear,
sensitivity, D-range, S/N and other characteristics
have been greatly improved compared with the
ICX039BNB. High sensitivity and low dark current
are achieved through the adoption of Ye, Cy, Mg and
G complementary color mosaic filters and HAD
(Hole-Accumulation Diode) sensors.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time. Also, this outline is miniaturized by using
original package.
This chip is compatible with and can replace the
ICX039BNB.
16 pin DIP (Ceramic)
Pin 1
2
V
12
Features
Low smear (–20dB compared with the ICX039BNB)
3
H 40
Pin 9
High sensitivity (+3.0dB compared with the ICX039BNB)
Optical black position
High D range (+2.5dB compared with the ICX039BNB)
High S/N
(Top View)
High resolution and low dark current
Excellent antiblooming characteristics
Ye, Cy, Mg, and G complementary color mosaic filters on chip
Continuous variable-speed shutter
Substrate bias:
Adjustment free (external adjustment also possible with 6 to 14V)
Reset gate pulse:
5Vp-p adjustment free (drive also possible with 0 to 9V)
Horizontal register:
5V drive
Maximum package dimensions: φ13.2mm
Device Structure
Interline CCD image sensor
Image size:
Diagonal 8mm (Type 1/2)
Number of effective pixels: 752 (H) x 582 (V) approx. 440K pixels
Total number of pixels: 795 (H) x 596 (V) approx. 470K pixels
Chip size:
7.95mm (H) x 6.45mm (V)
Unit cell size:
8.6µm (H) x 8.3µm (V)
Optical black:
Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction : Front 12 pixels, rear 2 pixels
Number of dummy bits: Horizontal 22
Vertical 1 (even fields only)
Substrate material:
Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96128C99

1 page




ICX039DNB pdf
ICX039DNB
Clock Voltage Conditions
Item Symbol
Readout clock voltage VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,
VVL3, VVL4
VφV
Vertical transfer clock
voltage
I VVH1 – VVH2 I
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
Horizontal transfer
clock voltage
VφH
VHL
Reset gate clock
voltage1
VRGL
VφRG
VRGLH – VRGLL
Substrate clock voltage VφSUB
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
14.55 15.0 15.45 V
1
–0.05 0 0.05 V
2 VVH = (VVH1 + VVH2)/2
–0.2 0 0.05 V
2
–9.6 –9.0 –8.5 V
2 VVL = (VVL3 + VVL4)/2
8.3 9.0 9.65 Vp-p
0.1 V
–0.25
0.1 V
–0.25
0.1 V
0.5 V
0.5 V
0.5 V
0.5 V
4.75 5.0 5.25 Vp-p
–0.05 0 0.05 V
1 V
4.5 5.0 5.5 Vp-p
0.8 V
23.0 24.0 25.0 Vp-p
2
2
2
2
2
2
2
2
3
3
4
4
4
5
VφV = VVHn – VVLn (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Low-level coupling
1 Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven
with the following specifications.
Item
Reset gate clock
voltage
Symbol
VRGL
VφRG
Min.
Typ.
Max.
Unit
Waveform
diagram
–0.2 0 0.2 V
4
8.5 9.0 9.5 Vp-p
4
Remarks
–5–

5 Page





ICX039DNB arduino
ICX039DNB
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions. (when used with substrate bias external adjustment, set the substrate voltage to the
value indicated on the device.)
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output
or chroma signal output of the measurement system.
Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals
Cy Ye Cy Ye
As shown in the left figure, fields are read out. The charge is
A1 mixed by pairs such as A1 and A2 in the A field. (pairs such
G Mg G Mg
as B in the B field)
B
Cy Ye Cy Ye
As a result, the sequence of charges output as signals from
Mg G Mg G
A2 the horizontal shift register (Hreg) is, for line A1, (G + Cy),
(Mg + Ye), (G + Cy), and (Mg + Ye).
Hreg
Color Coding Diagram
These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed
by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words,
the approximation:
Y = {(G + Cy) + (Mg + Ye)} × 1/2
= 1/2 {2B + 3G + 2R}
is used for the Y signal, and the approximation:
R – Y = {(Mg + Ye) – (G + Cy)}
= {2R – G}
is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are
(Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye).
The Y signal is formed from these signals as follows:
Y = {(G + Ye) + (Mg + Cy)} × 1/2
= 1/2 {2B + 3G + 2R}
This is balanced since it is formed in the same way as for line A1.
In a like manner, the chroma (color difference) signal is approximated as follows:
– (B – Y) = {(G + Ye) – (Mg + Cy)}
= – {2B – G}
In other words, the chroma signal can be retrieved according to the sequence of lines from R – Y and – (B – Y)
in alternation. This is also true for the B field.
– 11 –

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