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PDF FDMA1027P Data sheet ( Hoja de datos )

Número de pieza FDMA1027P
Descripción Dual P-Channel PowerTrench MOSFET
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FDMA1027P Hoja de datos, Descripción, Manual

October 2005
FDMA1027P
Dual P-Channel PowerTrench® MOSFET
General Description
This device is designed specifically as a single package
solution for the battery charge switch in cellular handset
and other ultra-portable applications. It features two
independent P-Channel MOSFETs with low on-state
resistance for minimum conduction losses. When
connected in the typical common source configuration,
bi-directional current flow is possible.
The MicroFET 2x2 package offers exceptional thermal
performance for it's physical size and is well suited to
linear mode applications.
PIN 1
S1 G1 D2
D1 D2
D1 G2 S2
MicroFET
Features
–3.0 A, –20V. RDS(ON) = 120 m@ VGS = –4.5V
RDS(ON) = 160 m@ VGS = –2.5V
RDS(ON) = 240 m@ VGS = –1.8V
Low profile – 0.8 mm maximum – in the new package
MicroFET 2x2 mm
S1 1
G1 2
D2 3
6 D1
5 G2
4 S2
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol
VDSS
VGSS
ID
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current – Continuous
– Pulsed
(Note 1a)
PD
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient
RθJA Thermal Resistance, Junction-to-Ambient
RθJA Thermal Resistance, Junction-to-Ambient
RθJA Thermal Resistance, Junction-to-Ambient
(Note 1a)
(Note 1b)
(Note 1c)
(Note 1d)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
027
FDMA1027P
7 in
Ratings
–20
±8
–2.2
–6
1.4
0.7
–55 to +150
Units
V
V
A
W
°C
86 (Single Operation)
173 (Single Operation)
69 (Dual Operation)
151 (Dual Operation)
°C/W
Tape width
8 mm
Quantity
3000 units
©2005 Fairchild Semiconductor Corporation
FDMA1027P Rev C1 (W)

1 page




FDMA1027P pdf
Typical Characteristics
5
ID = -3.0A
4
3
2
VDS = -5V
-15V
-10V
1
0
012345
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
100
10
RDS(ON) LIMIT
1
VGS = -4.5V
0.1 SINGLE PULSE
RθJA = 173oC/W
TA = 25oC
100us
1ms
10ms
100ms
1s
10s
DC
0.01
0.01
0.1 1 10
VDS, DRAIN-SOURCE VOLTAGE (V)
100
Figure 9. Maximum Safe Operating Area.
700
f = 1MHz
600 VGS = 0 V
500
400
Ciss
300
200
100
Crss
0
0
Coss
4 8 12 16
-VDS, DRAIN TO SOURCE VOLTAGE (V)
20
Figure 8. Capacitance Characteristics.
50
SINGLE PULSE
RθJA = 173°C/W
40 TA = 25°C
30
20
10
0
0.0001 0.001 0.01
0.1
1
10 100 1000
t1, TIME (sec)
Figure 10. Single Pulse Maximum Power
Dissipation.
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
SINGLE PULSE
RθJA(t) = r(t) * RθJA
RθJA =173 °C/W
P(pk)
t1
t2
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
0.01
0.0001
0.001
0.01
0.1 1
t1, TIME (sec)
10 100
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
1000
FDMA1027P Rev C1 (W)

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