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PDF 25PPC405EP Data sheet ( Hoja de datos )
| Número de pieza | 25PPC405EP | |
| Descripción | IBM25PPC405EP | |
| Fabricantes | IBM Microelectronics | |
| Logotipo |  |
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
www.DataSheet4U.com
Features
• IBM PowerPC 405 32-bit RISC processor core
operating up to 266MHz with 16KB D- and I-
caches
• PC-133 synchronous DRAM (SDRAM) interface
- 32-bit interface for non-ECC applications
• 4KB on-chip memory (OCM)
• External peripheral bus
- Flash ROM/Boot ROM interface
- Direct support for 8- or 16-bit SRAM and
external peripherals
- Up to five devices
• DMA support for memory and UARTs.
- Scatter-gather chaining supported
- Four channels
- Internal or external PCI Bus Arbiter
• Two Ethernet 10/100Mbps (full-duplex) ports
with media independent interface (MII)
• Programmable interrupt controller supports
seven external and 19 internal edge triggered or
level-sensitive interrupts
• Programmable timers
• Software accessible event counters
• Two serial ports (16750 compatible UART)
• One IIC interface
• General purpose I/O (GPIO) available
• Supports JTAG for board level testing
• Internal processor local Bus (PLB) runs at
SDRAM interface frequency
• PCI Revision 2.2 compliant interface (32-bit, up
to 66MHz)
- Asynchronous PCI Bus interface
• Supports PowerPC processor boot from PCI
memory
Description
Designed specifically to address embedded
applications, the PowerPC 405EP (PPC405EP)
provides a high-performance, low-power solution
that interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation requirements.
This chip contains a high-performance RISC
processor core, SDRAM controller, PCI bus
interface, Ethernet interface, control for external
ROM and peripherals, DMA with scatter-gather
support, serial ports, IIC interface, and general
purpose I/O.
Technology: IBM CMOS SA-27E, 0.18 µm
(0.11 µm Leff)
Package: 31mm, 385-ball, enhanced plastic ball
grid array (E-PBGA)
Power (typical): 1.2W at 200MHz
10/22/02
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
1
1 page  
PowerPC 405EP Embedded Processor Data Sheet
www.DataSheet4U.com
PPC405EP Embedded Controller Functional Block Diagram
Preliminary
Universal
Interrupt
Controller
16KB
D-Cache
Clock
Control
Reset
Power
Mgmt
Timers
MMU
DOCM
IOCM
PPC405
Processor Core
JTAG
DCU
Trace
ICU
OCM
SRAM
OCM
Control
DCR Bus
Event
Counters
DCRs
GPIO
IIC
GPT
UART
x2
16KB Arb
I-Cache
On-chip Peripheral Bus (OPB)
DMA
Controller
(4-Channel)
OPB
Bridge
MAL
Ethernet
x2
Arb Processor Local Bus (PLB)
SDRAM
Controller
13-bit addr
32-bit data
External
Bus
Controller
29-bit addr
16-bit data
PCI Bridge
66 MHz max (async)
MII
The PPC405EP is designed using the IBM Microelectronics Blue LogicTM methodology in which major
functional blocks are integrated together to create an application-specific ASIC product. This approach
provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
10/22/02
5
5 Page 
PowerPC 405EP Embedded Processor Data Sheet
www.DataSheet4U.com
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocol
• Programmable error recovery
Preliminary
General Purpose IO (GPIO) Controller
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus
master accesses
• All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
capabilities acts as a GPIO or is used for another purpose.
• Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, three-
stated if output bit is 1)
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between
the various sources of interrupts and the local PowerPC processor.
Features include:
• Supports seven external and 19 internal interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Non-critical or critical interrupt to processor core
• Programmable critical interrupt priority ordering
• Programmable critical interrupt vector for faster vector processing
10/100 Mbps Ethernet MAC
• Two ports capable of handling full/half duplex 100Mbps and 10Mbps operation
• Uses the medium independent interface (MII) to the physical layer (PHY not included on chip)
JTAG
• IEEE 1149.1 test access port
• IBM RISCWatch debugger support
• JTAG Boundary Scan Description Language (BSDL)
10/22/02
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 25PPC405EP.PDF ] | |
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