PDF ICS952606 Data sheet ( Hoja de datos )

Número de pieza	ICS952606
Descripción	Programmable Timing Control Hub for Next Gen P4 processor
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. ICS952606 Programmable Timing Control Hub™ for Next Gen P4™ processor Recommended Application: CK409 48-pin part Output Features: • 2 - 0.7V current-mode differential CPU pairs • 1 - 0.7V current-mode differential CPU pairs for ITP • 1 - 0.7V current-mode differential SRC pair • 9 - PCI (33MHz) • 1 - USB, 48MHz • 1 - DOT, 48MHz • 2 - REF, 14.318MHz • 3 - 3V66, 66.66MHz Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA • Supports spread spectrum modulation, 0 to -0.5% down spread and +/- 0.25% center spread • Supports CPU clks up to 400MHz in test mode • Uses external 14.318MHz crystal • Supports undriven differential CPU, SRC pair in PD# for power management. • 1 - 3V66/VCH, selectable 48MHz or 66MHz Key Specifications: • CPU/SRC outputs cycle-cycle jitter < 125ps • 3V66 outputs cycle-cycle jitter < 250ps • PCI outputs cycle-cycle jitter < 250ps • CPU outputs skew: < 100ps Pin Configuration FSA/REF0 1 FSB/REF1 2 VDDREF 3 • +/- 300ppm frequency accuracy on CPU & SRC clocks X1 4 X2 5 GND 6 Functionality PCICLK_F0 7 PCICLK_F1 8 FS2 CPU SRC B6b5 FS_A FS_B MHz MHz 0 0 100.00 100/200 0 0 1 1 200.00 100/200 0 133.33 100/200 1 1 166.66 100/200 0 0 200.00 100/200 1 0 1 1 400.00 100/200 0 266.66 100/200 1 1 333.33 100/200 3V66 MHz 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 REF MHz 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 USB/ DOT MHz 48.00 48.00 48.00 48.00 48.00 48.00 48.00 48.00 PCICLK_F2 9 VDDPCI 10 GND 11 PCICLK0 12 PCICLK1 13 PCICLK2 14 PCICLK3 15 VDDPCI 16 GND 17 PCICLK4 18 PCICLK5 19 PD# 20 48MHz_DOT 21 48MHz_USB 22 GND 23 VDD48 24 48 VDDA 47 GND 46 IREF 45 CPUCLKT_ITP 44 CPUCLKC_ITP 43 GND 42 CPUCLKT1 41 CPUCLKC1 40 VDDCPU 39 CPUCLKT0 38 CPUCLKC0 37 GND 36 SRCCLKT 35 SRCCLKC 34 VDD 33 Vtt_Pwrgd# 32 SDATA 31 SCLK 30 3V66_0 29 3V66_1 28 GND 27 VDD3V66 26 3V66_2 25 3V66_3/VCH **120KW pull-down 48-pin SSOP 0717F—06/10/05 1 page Integrated Circuit Systems, Inc. Absolute Max Symbol Parameter VDD_A 3.3V Core Supply Voltage VDD_In 3.3V Logic Input Supply Voltage Ts Tambient Tcase Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection ESD prot human body model Min -0.5 -65 0 2000 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V °C °C °C V ICS952606 Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Input High Voltage Input Low Voltage Input High Current Input Low Current VIH 3.3V +/-5% 2 VIL 3.3V +/-5% VSS - 0.3 IIH VIN = VDD -5 IIL1 VIN = 0 V; Inputs with no pull-up -5 resistors IIL2 VIN = 0 V; Inputs with pull-up resistors -200 VDD + 0.3 0.8 5 V V uA uA uA Operating Supply Current IDD3.3OP Full Active, CL = Full load; 260.000 350 Powerdown Current IDD3.3PD all diff pairs driven all differential pairs tri-stated 31.000 0.300 35 12 Input Frequency3 Pin Inductance1 Fi Lpin VDD = 3.3 V 14.31818 7 Input Capacitance1 CIN COUT Logic Inputs Output pin capacitance 5 6 Clk Stabilization1,2 CINX TSTAB X1 & X2 pins From VDD Power-Up or de- assertion of PD# to 1st clock. 5 1.8 Modulation Frequency Triangular Modulation 30 33 Tdrive_PD# CPU output enable after PD# de-assertion 300 Tfall_Pd# PD# fall time of 5 Trise_Pd# PD# rise time of 5 1Guaranteed by design, not 100% tested in production. 2See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. mA mA mA MHz nH pF pF pF ms kHz us ns ns 3 1 1 1 1 1,2 1 1 1 2 0717F—06/10/05 5 5 Page Integrated Circuit Systems, Inc. ICS952606 General I2C serial interface information for the ICS952606 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) sends the data byte count = X • ICS clock will acknowledge • Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • Controller (host) will send start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) will send a separate start bit. • Controller (host) sends the read address D3 (H) • ICS clock will acknowledge • ICS clock will send the data byte count = X • ICS clock sends Byte N + X -1 • ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). • Controller (host) will need to acknowledge each byte • Controllor (host) will send a not acknowledge bit • Controller (host) will send a stop bit Index Block Write Operation Controller (Host) ICS (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK Byte N + X - 1 P stoP bit ACK Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK ACK ACK Data Byte Count = X Beginning Byte N N Not acknowledge P stoP bit Byte N + X - 1 0717F—06/10/05 11 11 Page

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