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PDF ICS952801 Data sheet ( Hoja de datos )

Número de pieza ICS952801
Descripción Programmable Timing Control HubTM for K8TM processor
Fabricantes Integrated Circuit Systems　
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No Preview Available ! ICS952801 Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
Programmable Timing Control Hub™ for K8™ processor
Recommended Application:
SiS755/760 style chipset for AMD K8 Processor
Output Features:
• 2 - Pairs of differential push-pull K8CPU outputs
• 8 - PCICLK @ 3.3V
• 2 - AGPCLK @ 3.3V
• 3 - REF @ 3.3V
• 2 - ZCLK @ 3.3V
• 1 - 24_48MHz @ 3.3V
• 1 - 48MHz @ 3.3V
Key Specifications:
• CPU Output Jitter <250ps
• AGP Output Jitter <250ps
• ZCLK Output Jitter <250ps
• PCI Output Jitter <500ps
Functionality
Bit4 Bit3 Bit2 Bit1 Bit0 CPU ZCLK AGP
FS4 FS3 FS2 FS1 FS0 MHz MHz MHz
0 0 0 0 0 200.00 66.67 66.67
0 0 0 0 1 200.00 100.00 66.67
0 0 0 1 0 200.00 133.33 66.67
0 0 0 1 1 200.00 166.67 66.67
0 0 1 0 0 233.33 66.67 66.67
0 0 1 0 1 233.33 93.33 66.67
0 0 1 1 0 233.33 133.33 66.67
0 0 1 1 1 233.33 175.00 70.00
0 1 0 0 0 266.67 66.67 66.67
0 1 0 0 1 266.67 106.67 66.67
0 1 0 1 0 266.67 133.33 66.67
0 1 0 1 1 266.67 160.00 66.67
0 1 1 0 0 293.34 73.34 73.33
0 1 1 0 1 293.34 117.34 73.33
0 1 1 1 0 293.34 146.66 73.33
0 1 1 1 1 293.34 176.00 73.33
1 0 0 0 0 133.33 66.67 66.67
1 0 0 0 1 133.33 100.00 66.67
1 0 0 1 0 133.33 133.33 66.67
1 0 0 1 1 133.33 166.67 66.67
1 0 1 0 0 166.67 66.67 66.67
1 0 1 0 1 166.67 100.00 66.67
1 0 1 1 0 166.67 133.33 66.67
1 0 1 1 1 166.67 166.67 66.67
1 1 0 0 0 202.00 67.34 67.33
1 1 0 0 1 202.00 101.00 67.33
1 1 0 1 0 202.00 134.66 67.33
1 1 0 1 1 202.00 168.34 67.33
1 1 1 0 0 220.00 73.34 73.33
1 1 1 0 1 220.00 110.00 73.33
1 1 1 1 0 220.00 146.66 73.33
1 1 1 1 1 220.00 183.34 73.33
Features/Benefits:
• QuadRomTM frequency selection.
• Selectable synchronous/asynchronous AGP/PCI/ZCLK
frequency
• Linear Programmable CPU output frequency.
• Linear Programmable AGP/PCI output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system if system
malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz referience input.
Pin Configuration
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
35.00
33.33
33.33
33.33
33.33
36.66
36.66
36.66
36.66
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
36.66
36.66
36.66
36.66
VDDREF 1
48 CPU_STOP#*
**FS0/REF0 2
47 GNDCPU
**FS1/REF1 3
46 CPUCLK8T1
**FS2/REF2 4
GNDREF 5
45 CPUCLK8C1
44 VDDCPU
X1 6
43 VDDCPU
X2 7
42 CPUCLK8T0
GNDZ 8
41 CPUCLK8C0
ZCLK0 9
ZCLK1 10
40 GNDCPU
39 AGND
VDDZ 11
*PCI_STOP# 12
**FS3/PCICLK_F0 13
**FS4/PCICLK_F1 14
VDDPCI 15
GNDPCI 16
PCICLK0 17
PCICLK1 18
PCICLK2 19
PCICLK3 20
PCICLK4 21
PCICLK5 22
38 AVDD
37 PD#*
36 GNDAGP
35 AGPCLK0
34 AGPCLK1
33 VDDAGP
32 SCLK
31 AVDD48
30 48MHz
29 24_48MHz/SEL24_48MHz*
28 GND48
27 SDATA
GNDPCI 23
26 PCICLK7
VDDPCI 24
25 PCICLK6
48-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
0719—01/22/03
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

1 page




ICS952801 pdf
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
Table1: QuadRom Frequency Selection Table
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
X X FS4 FS3 FS2 FS1 FS0
0 00 0 0 0 0
0 00 0 0 0 1
0 00 0 0 1 0
0 00 0 0 1 1
0 00 0 1 0 0
0 00 0 1 0 1
0 00 0 1 1 0
0 00 0 1 1 1
0 00 1 0 0 0
0 00 1 0 0 1
0 00 1 0 1 0
0 00 1 0 1 1
0 00 1 1 0 0
0 00 1 1 0 1
0 00 1 1 1 0
0 00 1 1 1 1
0 01 0 0 0 0
0 01 0 0 0 1
0 01 0 0 1 0
0 01 0 0 1 1
0 01 0 1 0 0
0 01 0 1 0 1
0 01 0 1 1 0
0 01 0 1 1 1
0 01 1 0 0 0
0 01 1 0 0 1
0 01 1 0 1 0
0 01 1 0 1 1
0 01 1 1 0 0
0 01 1 1 0 1
0 01 1 1 1 0
0 01 1 1 1 1
CPU
MHz
200.00
200.00
200.00
200.00
233.33
233.33
233.33
233.33
266.67
266.67
266.67
266.67
293.34
293.34
293.34
293.34
133.33
133.33
133.33
133.33
166.67
166.67
166.67
166.67
202.00
202.00
202.00
202.00
220.00
220.00
220.00
220.00
ZCLK
MHz
66.67
100.00
133.33
166.67
66.67
93.33
133.33
175.00
66.67
106.67
133.33
160.00
73.34
117.34
146.66
176.00
66.67
100.00
133.33
166.67
66.67
100.00
133.33
166.67
67.34
101.00
134.66
168.34
73.34
110.00
146.66
183.34
AGP
MHz
66.67
66.67
66.67
66.67
66.67
66.67
66.67
70.00
66.67
66.67
66.67
66.67
73.33
73.33
73.33
73.33
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
67.33
67.33
67.33
67.33
73.33
73.33
73.33
73.33
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
35.00
33.33
33.33
33.33
33.33
36.66
36.66
36.66
36.66
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
36.66
36.66
36.66
36.66
Spread
%
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
B24b2:1 =11
B24b2:1 =11
B24b2:1 =11
B24b2:1 =11
Spread Off
Spread Off
Spread Off
Spread Off
0719—01/22/03
5

5 Page





ICS952801 arduino
Integrated
Circuit
Systems, Inc.
I2C Table: Output Control Register
Byte 7
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
14
13
22
21
20
19
18
17
PCICLK_F1
PCICLK_F0
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Control
Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
ICS952801
Advance Information
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
I2C Table: Byte Count Register
Byte 8
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control
Function
Writing to this register
will configure how
many bytes will be read
back, default is 0F = 15
bytes.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1 PWD
-0
-0
-0
-0
-1
-1
-1
-1
I2C Table: Watchdog Timer Register
Byte 9
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
Control
Function
These bits represent
X*290ms the watchdog
timer will wait before it
goes to alarm mode.
Default is 16 X 290ms
=4.64 seconds
Type
RW
RW
RW
RW
RW
RW
RW
RW
I2C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Name
Control
Function
Bit 7
-
M/NEN
M/N Programming
Enable
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
WDEN
Reserved
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
Watchdog Enable
Reserved
Writing to these bit will
configure the safe
frequency as Byte4bit
2, (7:4), Byte 24bit(6:5)
0719—01/22/03
Type
RW
R
RW
RW
RW
RW
RW
RW
11
0 1 PWD
- -0
- -0
- -0
- -1
- -0
- -0
- -0
- -0
0
Disable
Disable
-
-
-
-
-
-
1
Enable
Enable
-
-
-
-
-
-
PWD
0
0
0
0
0
0
0
1

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