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PDF ICS952802 Data sheet ( Hoja de datos )

Número de pieza ICS952802
Descripción Programmable Timing Control Hu for P4 processor
Fabricantes Integrated Circuit Systems　
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Integrated
Circuit
Systems, Inc.
ICS952802
Advance Information
Programmable Timing Control Hub™ for P4™ processor
Recommended Application:
SiS755/760 style chipset for AMD K8 Processor
Output Features:
• 2 - Pairs of differential push-pull K8CPU outputs
• 10 - PCICLK @ 3.3V
• 2 - AGPCLK @ 3.3V
• 3 - REF @ 3.3V
• 2 - ZCLK @ 3.3V
• 1 - 24_48MHz @ 3.3V
• 1 - 12_48MHz @ 3.3V
• 1 - PCI_12MHz @ 3.3V
Key Specifications:
• CPU Output Jitter <250ps
• AGP Output Jitter <250ps
Features/Benefits:
• Selectable synchronous/asynchronous AGP/PCI/ZCLK
frequency
• Linear Programmable output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology and system reset function
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz reference input.
Functionality
Bit4 Bit3 Bit2 Bit1 Bit0 CPU ZCLK AGP
FS4 FS3 FS2 FS1 FS0 MHz MHz MHz
0 0 0 0 0 160.00 106.66 53.33
0 0 0 0 1 200.00 133.33 66.67
0 0 0 1 0 200.00 133.33 66.67
0 0 0 1 1 200.00 160.00 66.67
0 0 1 0 0 186.66 106.67 53.33
0 0 1 0 1 233.33 133.33 66.67
0 0 1 1 0 233.33 133.33 66.67
0 0 1 1 1 233.33 155.55 66.67
0 1 0 0 0 213.34 106.66 53.33
0 1 0 0 1 266.67 133.33 66.67
0 1 0 1 0 266.67 133.33 66.67
0 1 0 1 1 266.67 160.00 66.67
0 1 1 0 0 133.34 106.66 53.33
0 1 1 0 1 166.67 133.33 66.67
0 1 1 1 0 166.67 133.33 66.67
0 1 1 1 1 166.67 166.66 66.67
1 0 0 0 0 206.00 137.33 68.67
1 0 0 0 1 210.00 140.00 70.00
1 0 0 1 0 202.00 134.66 67.33
1 0 0 1 1 202.00 161.60 67.33
1 0 1 0 0 240.33 137.33 68.67
1 0 1 0 1 245.00 140.00 70.00
1 0 1 1 0 235.66 134.67 67.33
1 0 1 1 1 235.66 157.11 67.33
1 1 0 0 0 106.66 106.66 53.33
1 1 0 0 1 133.33 133.33 66.67
1 1 0 1 0 133.33 133.33 66.67
1 1 0 1 1 133.33 177.77 66.67
1 1 1 0 0 171.67 137.33 68.67
1 1 1 0 1 175.00 140.00 70.00
1 1 1 1 0 168.34 134.66 67.33
1 1 1 1 1 168.34 168.33 67.33
PCI
MHz
26.66
33.33
33.33
33.33
26.66
33.33
33.33
33.33
26.66
33.33
33.33
33.33
26.66
33.33
33.33
33.33
34.33
35.00
33.66
33.66
34.33
35.00
33.66
33.66
26.66
33.33
33.33
33.33
34.33
35.00
33.66
33.66
Pin Configuration
VDDREF 1
48 CPU_STOP#/Reset#*
*FS0/REF0 2
47 GNDCPU
**FS1/REF1 3
46 CPUCLK8T1
**FS2/REF2 4
GNDREF 5
45 CPUCLK8C1
44 VDDCPU
X1 6
43 VDDCPU
X2 7
42 CPUCLK8T0
GNDZ 8
ZCLK0 9
ZCLK1 10
VDDZ 11
*PCI_STOP#/PCICLK8 12
41 CPUCLK8C0
40 GNDCPU
39 AGND
38 AVDD
37 PD#*
**FS3/PCICLK_F0 13
**FS4/PCICLK_F1 14
36 GNDAGP
35 AGPCLK0
VDDPCI 15
GNDPCI 16
PCICLK0 17
PCICLK1 18
PCICLK2 19
PCICLK3 20
PCICLK4 21
PCICLK5 22
34 AGPCLK1
33 VDDAGP
32 SCLK
31 AVDD48
30 12_48MHz/SEL12_48#**
29 24_48MHz/SEL24_48#*~
28 GND48
27 SDATA
GNDPCI 23
26 PCICLK7/12MHz/SELPCI_12#**
VDDPCI 24
25 PCICLK6/SEL_Reset#*
48-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This Output has 1.5X Drive Strength
0731—09/18/02
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

1 page




ICS952802 pdf
Integrated
Circuit
Systems, Inc.
ICS952802
Advance Information
Table1: Frequency Selection Table
Bit4 Bit3 Bit2 Bit1 Bit0 CPU
FS4 FS3 FS2 FS1 FS0 MHz
0 0 0 0 0 160.00
0 0 0 0 1 200.00
0 0 0 1 0 200.00
0 0 0 1 1 200.00
0 0 1 0 0 186.66
0 0 1 0 1 233.33
0 0 1 1 0 233.33
0 0 1 1 1 233.33
0 1 0 0 0 213.34
0 1 0 0 1 266.67
0 1 0 1 0 266.67
0 1 0 1 1 266.67
0 1 1 0 0 133.34
0 1 1 0 1 166.67
0 1 1 1 0 166.67
0 1 1 1 1 166.67
1 0 0 0 0 206.00
1 0 0 0 1 210.00
1 0 0 1 0 202.00
1 0 0 1 1 202.00
1 0 1 0 0 240.33
1 0 1 0 1 245.00
1 0 1 1 0 235.66
1 0 1 1 1 235.66
1 1 0 0 0 106.66
1 1 0 0 1 133.33
1 1 0 1 0 133.33
1 1 0 1 1 133.33
1 1 1 0 0 171.67
1 1 1 0 1 175.00
1 1 1 1 0 168.34
1 1 1 1 1 168.34
ZCLK
MHz
106.66
133.33
133.33
160.00
106.67
133.33
133.33
155.55
106.66
133.33
133.33
160.00
106.66
133.33
133.33
166.66
137.33
140.00
134.66
161.60
137.33
140.00
134.67
157.11
106.66
133.33
133.33
177.77
137.33
140.00
134.66
168.33
AGP
MHz
53.33
66.67
66.67
66.67
53.33
66.67
66.67
66.67
53.33
66.67
66.67
66.67
53.33
66.67
66.67
66.67
68.67
70.00
67.33
67.33
68.67
70.00
67.33
67.33
53.33
66.67
66.67
66.67
68.67
70.00
67.33
67.33
PCI
MHz
26.66
33.33
33.33
33.33
26.66
33.33
33.33
33.33
26.66
33.33
33.33
33.33
26.66
33.33
33.33
33.33
34.33
35.00
33.66
33.66
34.33
35.00
33.66
33.66
26.66
33.33
33.33
33.33
34.33
35.00
33.66
33.66
Spread
%
0.3% Center
0-0.5% Down
0.3% Center
0.3% Center
0.3% Center
0-0.5% Down
0.3% Center
0.3% Center
0.3% Center
0-0.5% Down
0.3% Center
0.3% Center
0.3% Center
0-0.5% Down
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0-0.5% Down
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0.3% Center
0731—09/18/02
5

5 Page





ICS952802 arduino
Integrated
Circuit
Systems, Inc.
ICS952802
Advance Information
Table 3: 4-Steps Skew Programming Table
4 Step
0
1
MSB
0
0ps
500ps
-
1
250ps
750ps
-
LSB
-
-
-
Table 4: Asynchronous Frequency Selection Table
B18 bit2 B18 bit1 B18 bit0
VCO
ZCLK
0 0 0 Main PLL Main PLL
0 0 1 528 Main PLL
0 1 0 528 Main PLL
0 1 1 528 Main PLL
1 0 0 528 132
1 0 1 528 132
1 1 0 528 132
1 1 1 528 132
AGP
Main PLL
66
75.4
88
Main PLL
66
75.4
88
PCI
Main PLL
33
37.7
44
Main PLL
33
37.7
44
I2C Table: Group Skew Control Register
Byte 19
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
ZCLKSkw3
ZCLKSkw2
ZCLKSkw1
ZCLKSkw0
AGPSkw3
AGPSkw2
AGPSkw1
AGPSkw0
Control
Function
CPU-ZCLK Skew
Control
CPU-AGP Skew
Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
01
16-Steps Skew Control.
This byte will advance or
delay the skew by 100ps
per step
16-Steps Skew Control.
This byte will advance or
delay the skew by 100ps
per step
PWD
0
0
1
1
0
0
1
1
I2C Table: Group Skew Control Register
Byte 20
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
PCISkw3
PCISkw2
PCISkw1
PCISkw0
Reserved
Reserved
Reserved
Reserved
Control
Function
CPU-PCI Skew Control
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
01
16-Steps Skew Control.
This byte will advance or
delay the skew by 100ps
per step
--
--
--
--
PWD
0
0
0
0
0
0
0
0
0731—09/18/02
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