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PDF ICS952001 Data sheet ( Hoja de datos )
| Número de pieza | ICS952001 | |
| Descripción | Preliminary Product Previes | |
| Fabricantes | Integrated Circuit Systems | |
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Hay una vista previa y un enlace de descarga de ICS952001 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Programmable Timing Control Hub for P4 processor
Recommended Application:
SIS 645/650 style chipsets.
Output Features:
• 2 - Pairs of differential CPUCLKs (differential current mode)
• 1 - SDRAM @ 3.3V
• 8 - PCI @3.3V
• 2 - AGP @ 3.3V
• 2 - ZCLKs @ 3.3V
• 1- 48MHz, @3.3V fixed.
• 1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
• 3- REF @3.3V, 14.318MHz.
Features/Benefits:
• Programmable output frequency, divider ratios, output
rise/falltime, output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• For PC133 SDRAM system use the ICS9179-06 as the
memory buffer.
• For DDR SDRAM system use the ICS93705 or
ICS93722 as the memory buffer.
• Uses external 14.318MHz crystal.
Key Specifications:
• PCI - PCI output skew: < 500ps
• CPU - SDRAM output skew: < 1ns
• AGP - AGP output skew: <150ps
Functionality
B it 2 B it 7 B it 6 B it 5 B it 4 C P U S D R A M Z C LK
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(M H z )
66.67
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
80.00
80.00
95.00
95.00
66.67
(M H z )
66.67
100.00
200.00
133.33
150.00
125.00
160.00
133.33
200.00
166.67
166.67
133.33
133.33
95.00
126.67
66.67
(M H z )
66.67
66.67
66.67
66.67
60.00
62.50
66.67
80.00
66.67
62.50
71.43
66.67
66.67
63.33
63.33
50.00
AGP
(M H z )
66.67
66.67
66.67
66.67
60.00
62.50
66.67
66.67
66.67
62.50
83.33
66.67
66.67
63.33
63.33
50.00
Note: For additional margin testing frequencies, refer to Byte 4
952001 Rev A 01/24/02
Pin Configuration
VDDREF
**FS0/REF0
**FS1/REF1
**FS2/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
ZCLK1
VDDZ
*PCI_STOP#
VDDPCI
**FS3/PCICLK_F0
**FS4/PCICLK_F1
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDSD
47 SDRAM
46 GNDSD
45 CPU_STOP#*
44 CPUCLKT_1
43 CPUCLKC_1
42 VDDCPU
41 GNDCPU
40 CPUCLKT_0
39 CPUCLKC_0
38 IREF
37 GNDA
36 VDDA
35 SCLK
34 SDATA
33 PD#*/Vtt_PWRGD
32 GNDAGP
31 AGPCLK0
30 AGPCLK1
29 VDDAGP
28 VDDA48
27 48MHz
26 24_48MHz/MULTISEL*
25 GND48
48-Pin 300-mil SSOP and TSSOP
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
/2
CPU
DIVDER
Stop
48MHz
24_48MHz
REF (1:0)
2
2 CPUCLKT (1:0)
2 CPUCLKC (1:0)
SDATA
SCLK
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
MULTISEL
PD#/Vtt_PWRGD
Control
Logic
Config.
Reg.
ZCLK
DIVDER
PCI
DIVDER
Stop
AGP
DIVDER
ZCLK (1:0)
2
6 PCICLK (9:0)
PCICLK_F (1:0)
2
AGP (1:0)
2
I REF
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
VDDREF = Xtal, REF
VDDZ = ZCLK
1 page  
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Serial Configuration Command Bitmap
Bytes 0-3: Are reserved for external clock buffer.
Byte4: Functionality and Frequency Select Register (default = 0)
Bit
Bit 2
Bit 7:4
Bit 3
Bit 1
Bit 0
Description
Bit 2 Bit 7 Bit 6 Bit 5 Bit 4
FS4 FS3 FS2 FS1 FS0 CPU SDRAM ZCLK
0 0 0 0 0 66.67 66.67 66.67
000 0
1 100.00 100.00 66.67
0 0 0 1 0 100.00 200.00 66.67
0 0 0 1 1 100.00 133.33 66.67
00
10
0 100.00 150.00 60.00
00 10
1 100.00 125.00 62.50
0 0 1 1 0 100.00 160.00 66.67
0 0 1 1 1 100.00 133.33 80.00
0 1 0 0 0 100.00 200.00 66.67
0 10 0
1 100.00 166.67 62.50
0 1 0 1 0 100.00 166.67 71.43
0 1 0 1 1 80.00 133.33 66.67
0 1 1 0 0 80.00 133.33 66.67
0 110
1 95.00 95.00 63.33
0 1 1 1 0 95.00 126.67 63.33
0 1 1 1 1 66.67 66.67 50.00
1 0 0 0 0 105.00 140.00 70.00
10 0 0
1 100.90 100.90 67.27
1 0 0 1 0 108.00 144.00 72.00
1 0 0 1 1 100.90 134.53 67.27
10
10
0 112.00 149.33 74.67
10 1 0
1 133.33 100.00 66.67
1 0 1 1 0 133.33 133.33 66.67
1 0 1 1 1 133.33 166.67 66.67
1 1 0 0 0 100.00 133.00 80.00
1 10
0
1 100.00 100.00 80.00
1 1 0 1 0 100.00 166.67 83.33
1 1 0 1 1 133.33 160.00 80.00
1110
0 100.00 133.00 100.00
1110
1 100.00 100.00 100.00
1 1 1 1 0 100.00 166.67 100.00
1 1 1 1 1 133.33 160.00 100.00
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit , 2 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
AGP
66.67
66.67
66.67
66.67
60.00
62.50
66.67
66.67
66.67
62.50
83.33
66.67
66.67
63.33
63.33
50.00
70.00
67.27
72.00
67.27
74.67
66.67
66.67
66.67
66.67
66.67
62.50
66.67
66.67
66.67
62.50
66.67
PCI
33.33
33.33
33.33
33.33
30.00
31.25
33.33
33.33
33.33
31.25
41.67
33.33
33.33
31.67
31.67
25.00
35.00
33.63
36.00
33.63
37.33
33.33
33.33
33.33
33.33
33.33
31.25
33.33
33.33
33.33
31.25
33.33
PWD
Spread Precentage
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
00000
Note1
0
0
0
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Note: PWD = Power-Up Default
Third party brands and names are the property of their respective owners.
5
5 Page 
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
VIH
VIL
IIH
IIL1
IIL2
IDD3.3O P
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 30 pF; CPU @ 133 MHz
2
VSS-0.3
-5
-5
-200
VDD+0.3
0.8
5
280
Power Down
Supply Current
IDD3.3PD CL = 0 pF
25
Input frequency
Fi VDD = 3.3 V
Pin Inductance
Input Capacitance1
Lpin
CIN Logic Inputs
Cout Out put pin capacitance
Transition Time1
Settling Time1
Clk Stabilization1
CINX
Ttrans
Ts
TSTAB
X1 & X2 pins
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
Delay
tPZH,tPZH output enable delay (all outputs)
tPLZ,tPZH output disable delay (all outputs)
1Guaranteed by design, not 100% tested in production.
14.32
27
1
1
7
5
6
45
3
3
3
10
10
UNITS
V
V
mA
mA
mA
mA
mA
MHz
nH
pF
pF
pF
mS
mS
mS
nS
nS
Third party brands and names are the property of their respective owners.
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ICS952001.PDF ] | |
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